P60ARM-B Zarlink Semiconductor, Inc., P60ARM-B Datasheet - Page 93

• Manufacturer Part Number: P60ARM-B
• Description: 32-bit RISC microprocessor
• Manufacturer: Zarlink Semiconductor, Inc.

8.0 Boundary Scan Test Interface
The boundary-scan interface conforms to the IEEE Std. 1149.1- 1990, Standard Test Access Port and
Boundary-Scan Architecture (please refer to this standard for an explanation of the terms used in this
section and for a description of the TAP controller states.)
8.1 Overview
The boundary-scan interface provides a means of testing the core of the device when it is fitted to a circuit
board, and a means of driving and sampling all the external pins of the device irrespective of the core state.
This latter function permits testing of both the device's electrical connections to the circuit board, and (in
conjunction with other devices on the circuit board having a similar interface) testing the integrity of the
circuit board connections between devices. The interface intercepts all external connections within the
device, and each such ÒcellÓ is then connected together to form a serial register (the boundary scan register).
The whole interface is controlled via 5 dedicated pins: TDI , TMS , TCK , nTRST and TDO . Figure 32: Test
Access Port (TAP) Controller State Transitions shows the state transitions that occur in the TAP controller.
tms=1
tms=0
Test-Logic Reset
Run-Test/Idle
tms=0
Figure 32: Test Access Port (TAP) Controller State Transitions
tms=1
tms=0
tms=1
tms=1
Select-DR-Scan
Capture-DR
Update-DR
Pause-DR
Exit1-DR
Exit2-DR
Shift-DR
Boundary Scan Test Interface
tms=0
tms=0
tms=1
tms=0
tms=1
tms=1
tms=0
tms=0
tms=0
tms=1
tms=1
tms=0
tms=1
tms=1
Select-IR-Scan
Capture-IR
Update-IR
Pause-IR
Exit1-IR
Exit2-IR
Shift-IR
tms=0
tms=0
tms=1
tms=0
tms=1
tms=1
tms=0
tms=0
tms=0
tms=1
tms=1
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