P60ARM-B Zarlink Semiconductor, Inc., P60ARM-B Datasheet - Page 89

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P60ARM-B

Manufacturer Part Number
P60ARM-B
Description
32-bit RISC microprocessor
Manufacturer
Zarlink Semiconductor, Inc.
Datasheet
7.12 Coprocessor data transfer (from coprocessor to memory)
The ARM60 controls these instructions exactly as for memory to coprocessor transfers, with the one
exception that the nRW line is inverted during the transfer cycle. The cycle timings are show in Table 18:
Coprocessor Data Transfer Instruction Cycle Operations.
m registers
n registers
1 register
1 register
not ready
not ready
(m>1)
ready
(n>1)
ready
Cycle
n+m+1
n+m
n+1
n+1
n+1
1
2
1
2
n
1
2
n
1
2
n
Table 18: Coprocessor Data Transfer Instruction Cycle Operations
Address
pc+8
alu
pc+12
pc+8
pc+8
pc+8
pc+8
alu
pc+12
pc+8
alu
alu+•
alu+•
alu+•
pc+12
pc+8
pc+8
pc+8
pc+8
alu
alu+•
alu+•
alu+•
pc+12
nBW
1
1
1
1
1
1
1
1
1
1
1
1
1
1
1
1
1
1
1
1
nRW
0
1
0
0
0
0
1
0
1
1
1
1
0
0
0
0
1
1
1
1
CPdata
CPdata
CPdata
CPdata
CPdata
CPdata
CPdata
CPdata
CPdata
CPdata
(pc+8)
(pc+8)
(pc+8)
(pc+8)
Data
Instruction Cycle Operations
-
-
-
-
-
-
nMREQ
0
0
1
1
1
0
0
0
0
0
0
0
1
1
1
0
0
0
0
0
SEQ
0
0
0
0
0
0
0
0
1
1
1
0
0
0
0
0
1
1
1
0
nOPC
0
1
0
1
1
1
1
0
1
1
1
1
0
1
1
1
1
1
1
1
nCPI
0
1
0
0
0
0
1
0
1
1
1
1
0
0
0
0
1
1
1
1
CPA
0
1
0
0
0
0
1
0
0
0
0
1
0
0
0
0
0
0
0
1
CPB
85
0
1
1
1
1
0
1
0
0
0
0
1
1
1
1
0
0
0
0
1

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