P60ARM-B Zarlink Semiconductor, Inc., P60ARM-B Datasheet - Page 27

• Manufacturer Part Number: P60ARM-B
• Description: 32-bit RISC microprocessor
• Manufacturer: Zarlink Semiconductor, Inc.

4.4 Data processing
The instruction is only executed if the condition is true, defined at the beginning of this chapter. The
instruction encoding is shown in Figure 8: Data Processing Instructions .
The instruction produces a result by performing a specified arithmetic or logical operation on one or two
operands. The first operand is always a register (Rn). The second operand may be a shifted register (Rm) or
a rotated 8 bit immediate value (Imm) according to the value of the I bit in the instruction. The condition
codes in the CPSR may be preserved or updated as a result of this instruction, according to the value of the
S bit in the instruction. Certain operations (TST, TEQ, CMP, CMN) do not write the result to Rd. They are
used only to perform tests and to set the condition codes on the result and always have the S bit set. The
instructions and their effects are listed in Table 4: ARM Data Processing Instructions .
31
Cond
28
27
00
26
25
I
24
OpCode
Figure 8: Data Processing Instructions
21
20
S
19
Instruction Set - Data processing
Rn
16
15
Rd
12
Destination register
1st operand register
Set condition codes
Operation Code
Immediate Operand
Condition field
11
11
11
0 = do not alter condition codes
1 = set condition codes
0000 = AND - Rd:= Op1 AND Op2
0001 = EOR - Rd:= Op1 EOR Op2
0010 = SUB - Rd:= Op1 - Op2
0011 = RSB - Rd:= Op2 - Op1
0100 = ADD - Rd:= Op1 + Op2
0101 = ADC - Rd:= Op1 + Op2 + C
0110 = SBC - Rd:= Op1 - Op2 + C
1000 = TST - set condition codes on Op1 AND Op2
1001 = TEQ - set condition codes on Op1 EOR Op2
1010 = CMP - set condition codes on Op1 - Op2
1011 = CMN - set condition codes on Op1 + Op2
1100 = ORR - Rd:= Op1 OR Op2
1101 = MOV - Rd:= Op2
1110 = BIC - Rd:= Op1 AND NOT Op2
1111 = MVN - Rd:= NOT Op2
0 = operand 2 is a register
1 = operand 2 is an immediate value
Rotate
shift applied to Imm
0111 = RSC - Rd:= Op2 - Op1 + C
shift applied to Rm
Shift
8
Unsigned 8 bit immediate value
7
Operand 2
2nd operand register
4
Imm
- 1
- 1
3
Rm
0
0
0
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