S1D13503 Epson Electronics America, Inc., S1D13503 Datasheet - Page 34

• Manufacturer Part Number: S1D13503
• Description: S1d13503 Graphics Lcd Controller
• Manufacturer: Epson Electronics America, Inc.

Page 26
5.2 Summary of Configuration Options
S1D13503
X18A-A-001-08
The S1D13503 requires some configuration information on power-up. This information is provided through the SRAM
data lines VD[0...15]. The state of these pins are read on the falling edge of RESET and used to configure the following
options:
Note
The S1D13503 has internal pulldown resistors on these pins and therefore will be pulled down
and read on a logic “0” after RESET. If pullup resistors are required refer to Table 6-3, “Input
Specifications,” on page 27 for pulldown resistor values.
Example: If an ISA bus (no byte swap) with memory segment “A” and I/O location 300h are used, the corresponding
settings of VD15-VD0 would be:
Where x = don’t care; 1 = connected to pull-up resistor; 0 = no pull-up resistor
Pin Name
VD0
VD1
VD2
VD3
VD12-VD4
VD15-VD13
VD15-VD13
VD12-VD4
Pin Name
VD0
VD1
VD2
VD3
value on this pin at falling edge of RESET is used to configure:
1
16-bit host bus interface
Use direct-mapping for I/O accesses
MC68000 MPU interface
Swap of high and low data bytes in 16-bit bus
interface
Select I/O mapping address bits [9:1].
These nine bits are latched on power-up and are compared to the MPU address bits [9-1]. A
valid I/O cycle combined with a valid address will enable the internal I/O decoder. Therefore,
both types of I/O mapping are limited to even address boundaries to determine either the
absolute or indexed I/O address of the first register. Note that a “valid I/O cycle” includes
IOCS# being toggled low.
Select memory mapping address bits [3:1]
These three bits are latched on power-up and are compared to the MPU address bits [19-17]. A
valid memory cycle combined with a valid address will enable the internal memory decoder.
As only the three most significant bits of the address are compared, the maximum amount of
memory supported is 128K bytes. Note that a “valid memory cycle” includes MEMCS# being
toggled low.
When using 128K byte memory it must be mapped at an even address such that all 128K bytes
is available without a change in state on A17, as this would invalidate the internal compare
logic.
Table 5-7: I/O and Memory Addressing Example
11 0000 000
Register
Index
101
0
0
0
0
8-Bit ISA Bus
Table 5-6: Summary of Power On / Reset Options
Direct Mapping
11 0000 xxx
101
0
1
0
0
11 0000 000
Register
Index
101
1
0
0
0
0
8-bit host bus interface
Use internal index register for I/O accesses
MPU / Bus interface with memory accesses
controlled by a READY (WAIT#) signal
No byte swap of high and low data bytes in
16-bit bus interface
16-Bit ISA Bus
Direct Mapping
11 0000 xxx
101
1
1
0
0
Hardware Functional Specification
Epson Research and Development
Vancouver Design Center
Issue Date: 01/01/29
(1/0)