S1D13503 Epson Electronics America, Inc., S1D13503 Datasheet - Page 245

• Manufacturer Part Number: S1D13503
• Description: S1d13503 Graphics Lcd Controller
• Manufacturer: Epson Electronics America, Inc.

Epson Research and Development
Vancouver Design Center
2.1 PAL Equations
2.2 Additional Discrete Logic Description
2.3 S1D13503 Default Setup
2.3.1 Configuration Options
ISA Bus Interface Considerations
Issue Date: 01/01/30
The PAL is programmed with the following equations:
Note
A ’!’ placed before a signal name indicates a logic ’0’ state.
A ’&’ indicates a logic ’AND’ function.
1.
2.
3.
Note
The MSBs of the address (A23:A20) need not be externally decoded if using SMEMW# and SMEMR#
as they will only assert on addresses < 1Mb.
1.
2.
The S1D13503 latches the state of the SRAM data bus during RESET to determine the power-on configuration. The chip
has internal pull-down resistors and therefore external pull-ups are only necessary when requiring a ’1’ state, see below.
1.
2.
3.
4.
5.
6.
Where 1 = pull-up with a 10K resistor; 0 = no pull-up resistor
As stated above, the default I/O address is from 0310h to 0311h. The S1D13503 provides internal decoding of ad-
dress bits A0 to A9, therefore minimal external circuitry is necessary to provide signals IOCS# and IOCS16#
IOCS# is required by the S1D13503 to indicate a valid I/O cycle. In an ISA bus environment, valid I/O decoding
must include addresses A15-A0. As A0-A9 are decoded internally, the equation must only guarantee that addresses
A10-15 must all be ’0’ and AEN must also be ’0’.
IOCS# = !(!AEN & !A15 & !A14 & !A13 & !A12 & !A11 & !A10)
As the S1D13503 is capable of 16-bit I/O access, the IOCS16# bus signal must be driven externally to indicate such a
cycle. As stated in the ISA specification, the IOCS16# is a straight address decode without qualification.
IOCS16EN# = !(!IOCS# & A9 & A8 & !A7 & !A6 & !A5 & A4 & !A3 & !A2 & !A1)
With 128Kbytes of display memory and A17 to A19 decoded internally to S1D13503;
MEMCS# = !REFRESH
As shown in Figure 1, the 74LS688 is configured as a memory decoder with valid addresses between 0C0000h and
0DFFFFh. This provides the MEMCS16# signal allowing for 16-bit memory cycles. As stated in the ISA specifica-
tion, the MEMCS16# is a straight address decode without qualification.
The 74LS09 is used simply to provide the Open-Collector outputs necessary for the IOCS16# and MEMCS16# sig-
nals.
VD15 - VD13 = 110
VD12 - VD4 = 110001000
VD3 = 0
VD2 = 0
VD1 = 0
VD0 = 1
memory decoding for locations $C and $D segments
I/O decoding for locations 0310h and 0311h (1100010000b - 1100010001b)
No byte swap of high and low bytes
ISA Bus interface, i.e. non- MC68K interface
Indexed I/O
16-bit bus interface
X18A-G-003-05
S1D13503
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