S1D13503 Epson Electronics America, Inc., S1D13503 Datasheet - Page 24

• Manufacturer Part Number: S1D13503
• Description: S1d13503 Graphics Lcd Controller
• Manufacturer: Epson Electronics America, Inc.

Page 16
3.5.5 Look-Up Table
3.5.6 Port Decoder
3.5.7 Memory Decoder
3.5.8 Data Bus Conversion
3.5.9 Address Generator
3.5.10 MPU / CRT Selector
3.5.11 Display Data Formatter
3.5.12 Clock Inputs / Timing
3.5.13 SRAM Interface
S1D13503
X18A-A-001-08
The Look-Up Table contains three 16x4-bit wide palettes. In gray shade modes, the “green” palette can be configured for
the re-mapping of 16 possible shades of gray. In color modes, all three palettes can be configured for the re-mapping of
4096 possible colors.
According to configuration settings VD1, VD12 - VD4, IOCS# and address lines AB9-1, the Port Decoder validates a given
I/O cycle.
According to configuration settings VD15 - VD13, MEMCS# and address lines AB19-17, the Memory Decoder validates
a given memory cycle.
According to configuration setting VD0, Data Bus Conversion maps the external data bus, either 8-bit or 16-bit, into the
internal odd and even data bus.
The Address Generator generates display refresh addresses to be used to access display memory.
The MPU / CRT Selector grants access to the display memory from either the MPU or the display refresh circuitry.
The Display Data Formatter reads in the display data from the display memory and outputs the correct format for all
supported gray shade and color selections.
Clock Inputs / Timing generates the internal master clock according to gray-level / color selected and display memory
interface. The master clock (MCLK) can be:
Pixel clock = input clock = f
The SRAM Interface generates the necessary signals to interface to the Display Memory (SRAM).
- MCLK = input clock
- MCLK = 1/2 input clock
- MCLK = 1/4 input clock.
OSC.
Hardware Functional Specification
Epson Research and Development
Vancouver Design Center
Issue Date: 01/01/29