S1D13503 Epson Electronics America, Inc., S1D13503 Datasheet - Page 141

• Manufacturer Part Number: S1D13503
• Description: S1d13503 Graphics Lcd Controller
• Manufacturer: Epson Electronics America, Inc.

Epson Research and Development
Vancouver Design Center
5.4 Split Screen
AUX[0A] bits 7-0 Screen 1 Display Line Count Bits [9:0]
AUX[0B] bits 1-0 These bits are the eight LSB of a 10-bit value used to determine the number of lines displayed for screen 1.
5.4.1 Description
Programming Notes and Examples
Issue Date: 01/01/30
AUX[0A] Screen 1 Display Line Count Register (LSB)
I/O address = 1010b, Read/Write.
Screen 1
Display
Line Count
Bit 7
AUX[0B] Screen 1 Display Line Count Register (MSB)
I/O address = 1011b, Read/Write.
n/a
This section describes how to create a split screen for both single and dual LCD panels. For single panel displays, the
Screen 1 Display Line Count Registers are used. For dual panel displays, the Screen 2 Display Start Address Registers are
used.
Registers
Note
See Section 4.2.2, “Display Start Address Registers” on page 37 for additional register descriptions.
A split screen is generally considered as the presentation of two different images on the screen. Image 1 is shown on the
top half and image 2 is shown on the bottom half of the screen. The system is always in split screen mode, on a single panel
image 2 is displayed off screen; on a dual panel image 2 becomes the lower half of the panel.
Screen 1
Display
Line Count
Bit 6
n/a
The remaining lines will automatically display from the screen 2 display start address. The 10-bit value
programmed is the number of display lines -1.
This register is used to enable the split screen display feature (single panel only) where two different
images can be displayed at the same time on one display.
For example; AUX[0A] = 20h for a 320x240 display system. The display will display 20h+1 = 33 lines on
the upper part of the screen as dictated by the screen 1 display start address registers (AUX[06] and
AUX[07]), and 240 - 33 = 207 lines will be displayed on the lower part of the screen as dictated by the
screen 2 display start address registers (AUX[08] and AUX[09]).
Two different images can be displayed when using a dual panel configuration by changing the screen 2 dis-
play start address. However, by using this method screen 2 is limited to the lower half of the display.
This register is ignored in dual panel mode.
Screen 1
Display
Line Count
Bit 5
n/a
Screen 1
Display
Line Count
Bit 4
n/a
Screen 1
Display
Line Count
Bit 3
n/a
Screen 1
Display
Line Count
Bit 2
n/a
Screen 1
Display
Line Count
Bit 1
Screen 1
Display
Line Count
Bit 9
Screen 1
Display
Line Count
Bit 0
Screen 1
Display
Line Count
Bit 8
X18A-G-002-06
S1D13503
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