MCC501RX166TD0B Motorola / Freescale Semiconductor, MCC501RX166TD0B Datasheet - Page 85

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MCC501RX166TD0B

Manufacturer Part Number
MCC501RX166TD0B
Description
Network Processor, 16 Processing Elements, 166MHz Core Operating Frequency, 5Gbps Max Throughput, 838-CBGA
Manufacturer
Motorola / Freescale Semiconductor
Datasheet
C-Port Confidential
(output)
(input)
MDCLK
M_ctl
MAn
MDn
MDn
Specifications
BMU Timing
Cycle 1
T
mdo
The BMU timing specifications are shown in
The BMU synchronous DRAM interface is PC100-compliant and designed to work with
industry standard SDRAM components with 12 or fewer address lines. The information
below is intended to provide the output, setup, and hold data required to design this
interface without duplicating the transaction waveform diagrams in SDRAM data sheets.
Figure 23 BMU Timing Diagram
Table 49 BMU Timing Description
*
Symbol Parameter
Tmc
Tmco
Tmao
Tmds
Tmdh
Tmdo
Tmdz
Tmdv
Not fully tested, values based on design/characterization.
T
T
mao
mco
Cycle 2
T
mc
BMU Cycle Time
BMU Ctrl Output
BMU Addr Output
BMU Data Setup
BMU Data Hold
BMU Data Output
BMU Data Clk to Tri*
BMU Data Clk to Driven*
T
mdz
Cycle 3
T
mds
Min
8.0
1.2
1.2
0.5
1.0
1.2
1.8
1.4
T
mdh
Figure 23
Typ
T
mdv
Cycle 4
and described in
Max
3.7
3.8
4.0
4.0
4.0
AC Timing Specifications
Preliminary Version — January 21, 2002
Unit
ns
ns
ns
ns
ns
ns
ns
ns
Cycle 5
Table
49.
85

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