MCC501RX166TD0B Motorola / Freescale Semiconductor, MCC501RX166TD0B Datasheet - Page 33

• Manufacturer Part Number: MCC501RX166TD0B
• Description: Network Processor, 16 Processing Elements, 166MHz Core Operating Frequency, 5Gbps Max Throughput, 838-CBGA
• Manufacturer: Motorola / Freescale Semiconductor

Table 11 OC-12 Signals Example (continued)
*
†
Table 12 PCI Signals
C-Port Confidential
System Interface Signals
Signal Name* Pin #†
CPn+3_2
CPn+3_3
CPn+3_4
CPn+3_5
CPn+3_6
Total Pins
Signal Name
PAD0 - PAD31
PCBEX0 - PCBEX3
PPAR
PFRAMEX
n can be 0, 4, 8, or 12
Reference
Executive Processor
Table 4
for pin numbers for a different cluster.
Table 4
Table 4
Table 4
Table 4
Table 4
Pin #
T22, R21, P21, T21, R20, P20, T20,
R19, Q20, S20, R18, P19, T19,
R17, P18, T18, R16, Q18, S18, S16,
P17, T17, R15, P16, T16, S14, Q16,
T15, R14, P15, T14, Q14
N21, N20, M20, O20
P14
K20
Total Type
1
1
1
1
1
28
The XP’s system interface manages the supervisory controls for the network interfaces, as
well as the set of pins that provide interfaces to other components in the system that are
not memories or network interfaces. It is also the primary interface used for initializing the
C-5 NP after reset. The XP signals include PCI signals, Serial interface signals, and PROM
interface signals.
PCI Signals
The PCI can be configured to support a 32bit PCI capable of operating at either 33MHz or
66MHz. The PCI is fully compliant with PCVI Specification revision 2.1.
the PCI signals.
LVTTL
LVTTL
LVTTL
LVTTL
nc
I/O
I
I
I
I
nc
Total Type
32
4
1
1
Label
RXD(4)
RXD(5)
RXD(6)
RXD(7)
nc
PCI
PCI
PCI
PCI
Signal Description
Receive Data
Receive Data
Receive Data
Receive Data (most significant bit)
nc
I/O
I/O
I/O
I/O
I/O
Signal Description
Multiplexed Address/Data Bus. These signals are
multiplexed address and data bits. The C-5 NP
receives addresses as target and drives addresses as
master. It drives the data and receives read data as
master.
Command byte enables. These signals are
multiplexed command and byte enabled signals.
The C-5 NP receives byte enables as target and drives
byte enables as master.
Parity. This signal carries even parity for AD and CBE#
pins. It has the same receive and drive characteristics
as the address and data bus, except that it is one PCI
cycle later.
Cycle frame
Pin Descriptions Grouped by Function
Preliminary Version — January 21, 2002
Table 12
describes
33