MCC501RX166TD0B Motorola / Freescale Semiconductor, MCC501RX166TD0B Datasheet - Page 28

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MCC501RX166TD0B

Manufacturer Part Number
MCC501RX166TD0B
Description
Network Processor, 16 Processing Elements, 166MHz Core Operating Frequency, 5Gbps Max Throughput, 838-CBGA
Manufacturer
Motorola / Freescale Semiconductor
Datasheet
28
Table 8 Gigabit Ethernet (GMII/MII) Signals One Cluster Example
January 21, 2002— Preliminary Version
Signal Name* Pin #† Total Type
CPn_0
CPn_1
CPn_2
CPn_3
CPn_4
CPn_5
CPn_6
CPn+1_0
CPn+1_1
CPn+1_2
CPn+1_3
CPn+1_4
CPn+1_5
C
HAPTER
2: S
Table 4
Table 4
Table 4
Table 4
Table 4
Table 4
Table 4
Table 4
Table 4
Table 4
Table 4
Table 4
Table 4
IGNAL
D
ESCRIPTIONS
1
1
1
1
1
1
1
1
1
1
1
1
1
Figure 3 GMII/TBI Transmit and Receive Pin Configurations
The unused CP pins in the two cluster configurations should be wired to ground using a
resistor.
LVTTL
LVTTL
LVTTL
LVTTL
LVTTL
LVTTL
LVTTL
nc
LVTTL
LVTTL
LVTTL
LVTTL
LVTTL
Single Cluster Mode
Pin Configuration
I/O
O
I
O
O
O
O
O
nc
I
O
O
O
O
Cluster
Cluster
Cluster
Cluster
0
1
2
3
Label
T_CLK
TCLKI
TXD(0)
TXD(1)
TXD(2)
TXD(3)
TX_EN
nc
COL
TXD(4)
TXD(5)
TXD(6)
TXD(7)
Tx
Rx
Tx
Rx
Tx
Rx
Tx
Rx
Signal Description
GMII Transmit Clock (125MHz). This clock is used to synchronize the
transmit data.
MII transmit clock. Transmit data aligned to this clock input from
phy in MII mode. 25 Mhz in 100BaseT, 2.5 in Mhz in 10BaseT
Transmit Data (byte-wide data, least significant bit)
Transmit Data
Transmit Data
Transmit Data
Transmit Enable. When asserted, the data on TXD is encoded and
transmitted on the twisted pair cable.
nc
Collision. Asserted when both RX_DV and TX_EN are valid during
half duplex operation.
Transmit Data
Transmit Data
Transmit Data
Transmit Data (byte-wide receive data, most significant bit)
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}
Port 1
Port 2
Port 3
Port 4
nc = not connected
Pin Configuration
Two Cluster Mode
Cluster
Cluster
Cluster
Cluster
0
1
2
3
Tx
Rx
nc
Tx
nc
Rx
Tx
Rx
nc
Tx
nc
Rx
}
}
Port 1
Port 2
C-Port Confidential

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