MCC501RX166TD0B Motorola / Freescale Semiconductor, MCC501RX166TD0B Datasheet - Page 27

• Manufacturer Part Number: MCC501RX166TD0B
• Description: Network Processor, 16 Processing Elements, 166MHz Core Operating Frequency, 5Gbps Max Throughput, 838-CBGA
• Manufacturer: Motorola / Freescale Semiconductor

Table 6 10/100 Ethernet Signals
*
C-Port Confidential
Signal Name* Pin #
CPn_0
CPn_1
CPn_2
CPn_3
CPn_4
CPn_5
CPn_6
Total Pins
n can be from 0 to 15. See
Table 4
Table 4
Table 4
Table 4
Table 4
Table 4
Table 4
Table
Total
1
1
1
1
1
1
1
7
4.
Gigabit Ethernet (GMII) Configuration
Gigabit Ethernet Media Independent Interface (GMII) is configured in one of two ways:
1 Use one CP cluster when density is more important than wire-speed performance
2 Use two CP clusters for wire-speed performance and additional processing power. You
Table 7
and transmit pin configurations by cluster.
Ethernet (GMII).
Table 7 Transmit and Receive Pin Combinations for Gigabit Ethernet and Fibre Channel
*
Cluster
0
1
2
3
Type
LVTTL
LVTTL
LVTTL
LVTTL
LVTTL
LVTTL
LVTTL
The Two Cluster Mode column lists typical configurations. Any cluster can be set up to either receive
or transmit. So you could configure a dual cluster mode where cluster 0 receives and cluster 3
transmits.
because you can then implement up to four Gigabit Ethernet ports per C-5 NP.
can implement up to two Gigabit Ethernet ports per C-5 NP.
lists the possible CP cluster combinations you can use and
I/O
O
I
O
O
I
I
O
Single Cluster Mode (TBI or GMII)
Port 1 Tx and Rx
Port 2 Tx and Rx
Port 3 Tx and Rx
Port 4 Tx and Rx
Label
REF_CLK
CRS_DV
TXD(0)
TXD(1)
RXD(0)
RXD(1)
TX_EN
Signal Description
Transmit and Receive Clock (50MHz)
Carrier Sense (CRS)/ Receive Data Valid (RX_DV). CRS indicates that
traffic is on the link, and is asserted if the signal is a 1 or an
alternating 1010... RX_DV indicates that a receive frame is in
progress and the data present on the RXD pins is valid. It is
asserted if this signal is a 1 for more than one cycle.
Transmit Data 0 (first on wire)
Transmit Data 1 (second on wire)
Receive Data 0 (first on wire)
Receive Data 1 (second on wire)
Transmit Enable. When asserted, the data on TXD is encoded and
transmitted on the twisted pair cable.
Table 8
Pin Descriptions Grouped by Function
lists the signals and pinouts for Gigabit
Two Cluster Mode (GMII)*
Port 1 Tx
Port 1 Rx
Port 2 Tx
Port 2 Rx
Preliminary Version — January 21, 2002
Figure 3
shows receive
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