MCC501RX166TD0B Motorola / Freescale Semiconductor, MCC501RX166TD0B Datasheet
MCC501RX166TD0B
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MCC501RX166TD0B Summary of contents
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C-5 Network Processor TM Data Sheet Supporting C-5 Network Processor Version D0 Feature List Complete programmability • Programmability at all levels of the protocol stack: Layers 2-7 • Examples of C-5 enabled systems: – Multiservice Access Platforms (MSAPs) – Optical ...
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C-Port Corporation Copyright © 2002 C-Port Corporation. All rights reserved. No part of this 120 Water Street documentation may be reproduced in any form or by any means or used to make any N. Andover, MA derivative work (such as ...
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Contents List of Figures List of Tables About This Guide Data Sheet Description and Organization . . . . . . . . . . . . . . . . . . . . . . . . . ...
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C ONTENTS Signals Grouped by Pin Number . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . ...
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C 4 Mechanical Specifications HAPTER Package Views . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . ...
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C ONTENTS January 21, 2002— Preliminary Version C-Port Confidential ...
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List of Figures 1 C-5 Network Processor Block Diagram 2 Pin Locations (Bottom View) 3 GMII/TBI Transmit and Receive Pin Configurations 4 PROM Interface Diagram . . . . . . . . . . . . . . . ...
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January 21, 2002 C-Port Confidential ...
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List of Tables 1 C-5 Network Processor Data Sheet Revision History 2 TLU SRAM Configurations . . . . . . . . . . . . . . . . . . . . . . . . . ...
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January 21, 2002 C-5 Network Processor Recommended Operating Conditions C-5 Network Processor DC Characteristics C-5 ...
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About This Guide Data Sheet This data sheet describes the C-5 Network processor, Version D0. It provides hardware Description and layout specifications including pinouts, memory configuration guidelines, timing Organization diagrams, power and power sequencing guidelines, thermal design guidelines, and mechanical ...
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BOUT HIS UIDE Table 1 C-5 Network Processor Data Sheet Revision History Revision Date June 12, 2000 June 14, 2000 July 17, 2000 August 8, 2000 January 21, 2002 — Preliminary Version Change Chapter 2 contains ...
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Table 1 C-5 Network Processor Data Sheet Revision History Revision Date March 26, 2001 C-Port Confidential Change Chapter 1 contains the following revisions: • Fabric Processor Interface Frequency changed from 100 MHz to 110 MHz thruoughout. • TLU interface memory ...
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BOUT HIS UIDE Table 1 C-5 Network Processor Data Sheet Revision History Revision Date October 1, 2001 January 21, 2002 January 21, 2002 — Preliminary Version Change Chapter 2 contains the following revisions: • LVTTL and ...
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Chapter 1 Functional Description Block Diagram The C-5 applications. interfaces. The following sections describe each component of the C-5 NP. For more information about the architecture of the C-5 NP, see the C-5 Network Processor Architecture Guide. Figure 1 C-5 ...
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The main components of the C-5 NP are: • • • • • • Channel Processors The C-5 NP contains sixteen programmable Channel Processors (CPs) that receive, process, and transmit network data. The number of CPs per port is ...
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Executive Processor The Executive Processor (XP) serves as a centralized computing resource for the C-5 NP and manages the system interfaces. The XP performs conventional supervisory tasks in the C-5 NP, including: • • • • • System Interfaces The ...
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Fabric Processor The Fabric Processor (FP) acts as a high-speed network interface port with advanced functionality. It allows the C interface to an application-specific switching solution internal to your design. The FP port supports the bidirectional transfer ...
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SDRAM devices that use 12 address lines. Internal address calculation paths limit the maximum memory size to 128MBytes. Only one physical bank of SDRAM is supported. Table Lookup Unit The Table Lookup Unit (TLU) performs table lookups in external ...
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The QMU’s external SRAM interface uses ZBT synchronous SRAMs organized in a single bank 128k, 32bit words. ...
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Chapter 2 Signal Descriptions Signal Summary There are ten functional groupings of signals in the C-5 network processor: • • • • • • • • • • Two of the sections (CPs and FP) are configurable, depending on the ...
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HAPTER IGNAL ESCRIPTIONS Pinout Diagram The C-5 NP contains 838 pins as shown in throughout the remaining chapter. Figure 2 Pin Locations (Bottom View ...
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Pin Descriptions The C-5 NP pins are categorized in groups, reflecting interfaces to the chip: Grouped by Function • • • • • • • • • • LVTTL and LVPECL C-5 NP pins are the following types: Specifications • ...
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HAPTER IGNAL ESCRIPTIONS Table 3 Clock and Reference Signals (continued) Signal Name CCLK6 CCLK7 CPREF‡ Total * SCLK and SCLKX must not be AC-coupled. † The frequencies specified for CCLK0 - CCLK7 allow full flexibility ...
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Table 4 CP Physical Interface Signals and Pins (Grouped by Clusters) Signal CP0_0 CP0_1 CP0_2 CP0_3 CP0_4 CP0_5 CP0_6 CP1_0 CP1_1 CP1_2 CP1_3 CP1_4 CP1_5 CP1_6 CP2_0 CP2_1 CP2_2 CP2_3 CP2_4 CP2_5 CP2_6 CP3_0 CP3_1 CP3_2 ...
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HAPTER IGNAL ESCRIPTIONS Table 4 CP Physical Interface Signals and Pins (Grouped by Clusters) (continued) Signal CP3_3 CP3_4 CP3_5 CP3_6 DS1/T1 Framer Interface Configuration Table 5 implement one serial Framer interface. Table 5 DS1/T1 Framer ...
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Table 6 10/100 Ethernet Signals Signal Name* Pin # Total Type CPn_0 Table 4 1 LVTTL CPn_1 Table 4 1 LVTTL CPn_2 Table 4 1 LVTTL CPn_3 Table 4 1 LVTTL CPn_4 Table 4 1 LVTTL CPn_5 Table 4 1 ...
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HAPTER IGNAL ESCRIPTIONS Figure 3 GMII/TBI Transmit and Receive Pin Configurations The unused CP pins in the two cluster configurations should be wired to ground using a resistor. Table 8 Gigabit Ethernet (GMII/MII) Signals One ...
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Table 8 Gigabit Ethernet (GMII/MII) Signals One Cluster Example (continued) Signal Name* Pin #† Total Type CPn+1_6 Table 4 1 LVTTL CPn+2_0 Table CPn+2_1 Table 4 1 LVTTL CPn+2_2 Table 4 1 LVTTL CPn+2_3 Table 4 1 ...
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HAPTER IGNAL ESCRIPTIONS The unused pins for the two cluster configurations should be wired down using a resistor. Table 9 Gigabit Ethernet and Fibre Channel TBI Signals Example Signal Name* Pin #† Total Type CPn_0 ...
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Table 9 Gigabit Ethernet and Fibre Channel TBI Signals Example (continued) Signal Name* Pin #† Total Type CPn+3_4 Table 4 1 LVTTL CPn+3_5 Table 4 1 LVTTL CPn+3_6 Table 4 1 LVTTL 28 Total Pins * n can be 0, ...
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HAPTER IGNAL ESCRIPTIONS SONET OC-12 Transceiver Interface Configuration SONET Optical Carrier (OC implemented by using one cluster of CPs. At any time within a cluster spends half its time performing receive ...
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Table 11 OC-12 Signals Example (continued) Signal Name* Pin #† Total Type CPn+3_2 Table 4 1 CPn+3_3 Table 4 1 CPn+3_4 Table 4 1 CPn+3_5 Table 4 1 CPn+3_6 Table Total Pins * n can be 0, ...
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HAPTER IGNAL ESCRIPTIONS Table 12 PCI Signals (continued) Signal Name Pin # PTRDYX L20 PIRDYX L19 PSTOPX K18 PDEVSELX N18 PPERRX M18 PSERRX L18 PCLK L15 PRSTX N17 PREQX L17 PGNTX N19 PIDSEL O18 PINTA ...
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Table 13 Serial Port Signals Signal Name SICL SIDA Total Pins PROM Interface Signals ...
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HAPTER IGNAL ESCRIPTIONS Figure 4 PROM Interface Diagram The PROM interface operates in the following manner (Note that two accesses are piplined together to execute one 32-bit fetch). The steps are shown in 1 The ...
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SPLD is deasserted for 22 SPCLK cycles, shifting the second PROM_DATA into the 9 SPLD is asserted for one SPCLK cycle, loading the second PROM_DATA into the Figure 5 PROM Interface Timing Outline XP PROM Interface outline Q< Q< ...
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HAPTER IGNAL ESCRIPTIONS Table 15 General System Interface Signal Signal Name Pin # Total Type XPUHOT J19 1 1 Total Pins Fabric Processor The FP consists of two logical signal interfaces: a receive data interface ...
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The following tables list the Fabric Interface pin mappings: • • • • Table 17 Utopia1*, 2*, 3 ATM Mode, C-5 Network Processor to Fabric Interface Pin Mapping Receive Signals C-5 Network Processor I/O Utopia FRXCTL0 Output RxEnb* FRXCTL1 Input ...
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HAPTER IGNAL ESCRIPTIONS Table 18 Utopia1*, 2*, 3 PHY Mode, C-5 Network Processor to Fabric Interface Pin Mapping Receive Signals C-5 Network Processor I/O Utopia FRXCTL6 Input TxPrty * cell size must be 4Byte aligned. ...
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Table 20 Power X Mode, C-5 Network Processor to Fabric Interface Pin Mapping Receive Signals C-5 Network Processor I/O Power X FRXCTL3 Input RxPrty[3] FRXCTL4 Input RxPrty[2] FRXCTL5 Input RxPrty[1] FRXCTL6 Input RxPrty[0] C-Port Confidential Pin Descriptions Grouped by Function ...
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HAPTER IGNAL ESCRIPTIONS BMU SDRAM Interface The BMU and SDRAM interface signals are described in Signals The BMU is designed to support SDRAM devices with 12 address lines. All 139 data lines and all 12 ...
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Table 21 BMU SDRAM Interface Signals (continued) Signal Name Pin # MRASX I20 MWEX J20 MCSX H20 MDQM H21 MDQML G14 MDCLK J17 Total Pins C-Port Confidential Pin Descriptions Grouped by Function Total Type I/O Signal Description 1 LVTTL O ...
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HAPTER IGNAL ESCRIPTIONS TLU SRAM Interface The TLU SRAM interface supports up to 32MBytes of SRAM at frequencies to 133MHz Signals using LVTTL signaling levels (in single bank-mode only) and SRAM technologies up to 64Mbits. ...
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QMU SRAM Interface The QMU signals are described in Signals core clock frequency. Table 24 QMU SRAM Interface Signals Signal Name Pin # QCPAR A10 QCLK G12 QCMD0 - QCMD15 B10, C10, D10, E10, F10, B11, D11, F11, A12, B12, ...
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HAPTER IGNAL ESCRIPTIONS Table 25 Power Supply Signals (continued) Signal Name Pin # VSS A5, A9, A13, A17, A21, A25, A29, C3, C7, C11, C15, C19, C23, C27, E1, E5, E9, E13, E17, E21, E25, ...
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Figure 6 Power and Ground Connections (Bottom View C-Port Confidential 1 ...
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HAPTER IGNAL ESCRIPTIONS Test Signals Test signals are described in Table 26 Miscellaneous Test Signals For JTAG, Scan, and Internal Test Routines Signal Name Pin # JTCK T11 JTMS* Z15 JTRSTX† X15 JTDI† AB15 JTDO ...
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Signals Grouped by The C-5 NP signals are listed by pin number in Pin Number Table 28 Signals Listed by Pin Number Pin ...
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HAPTER IGNAL ESCRIPTIONS Table 28 Signals Listed by Pin Number (continued) Pin ...
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Table 28 Signals Listed by Pin Number (continued) Pin C-Port Confidential Function Pin Function QDATA31 ...
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HAPTER IGNAL ESCRIPTIONS Table 28 Signals Listed by Pin Number (continued) Pin ...
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Table 28 Signals Listed by Pin Number (continued) Pin C-Port Confidential Function Pin Function M 1-29 ...
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HAPTER IGNAL ESCRIPTIONS Table 28 Signals Listed by Pin Number (continued) Pin ...
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Table 28 Signals Listed by Pin Number (continued) Pin C-Port Confidential Function Pin Function S 1-29 ...
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HAPTER IGNAL ESCRIPTIONS Table 28 Signals Listed by Pin Number (continued) Pin ...
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Table 28 Signals Listed by Pin Number (continued) Pin AA1 AA2 AA3 AA4 AA5 AA6 AA7 AA8 C-Port Confidential Function Pin Function Y 1-29 ...
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HAPTER IGNAL ESCRIPTIONS Table 28 Signals Listed by Pin Number (continued) Pin AB1 AB2 AB3 AB4 AB5 AB6 AB7 AB8 AC1 AC2 AC3 AC4 AC5 AC6 AC7 AC8 JTAG Support The C-5 NP contains JTAG ...
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JTAG Data Registers The C-5 NP contains the standard internal registers as specified in IEEE 1149.1. These registers are described in Table 29 JTAG Internal Register Descriptions Register Name Bypass Boundary Device Identification Boundary Scan Cell The C-5 NP boundary ...
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HAPTER IGNAL ESCRIPTIONS Figure 8 Cell Design That Can Be Used for Both Input and Output Pins IDcode Register The C-5 NP implements a standard 32bit JTAG identification register. value of the code for full ...
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JTAG Instruction The C-5 NP contains a 4bit instruction register. Register supported. Table 31 Instruction Register Instructions Instruction Mnemonic Extest Idcode Sample/Preload Highz Clamp Bypass Reserved* Reserved* Bypass Bypass Bypass Bypass Bypass Bypass Bypass Bypass * There are two reserved ...
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HAPTER IGNAL ESCRIPTIONS January 21, 2002— Preliminary Version C-Port Confidential ...
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Chapter 3 Electrical Specifications Absolute Maximum Table 32 Ratings beyond those listed may cause permanent damage to the device. These are stress ratings only and do not imply that operation under any conditions other than those listed under “Recommended Operating ...
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HAPTER LECTRICAL PECIFICATIONS Recommended The recommended operating conditions describe an environment the C-5 NP network Operating Conditions processor is expected to encounter during normal operation. recommended operating parameters for the C-5 NP. Table 33 C-5 ...
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DC Characteristics The DC electrical characteristics define the input operating conditions for proper operation and the output responses to applied DC signals and switch characteristics over specified voltage and temperature ranges. The DC electrical characteristics are specified within the recommended ...
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HAPTER LECTRICAL PECIFICATIONS Power Sequencing The VDD rail must be kept within 2.5V of the VDD33 rail. However, this rule can be violated for periods up to one second typical during power sequencing, ...
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Power and Thermal Table 36 Characteristics version (Revision D0) of the C-5 NP. Table 36 C-5 Network Processor Power and Thermal Characteristics Parameter Power Dissipation, P Maximum Junction Temperature, T Thermal Resistance, junction to case, Thermal Resistance, junction to ambient, ...
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HAPTER LECTRICAL PECIFICATIONS 2 Thermal performance specifications based on following conditions: 3 Effective Thermal Resistance ( Figure 10 Thermal Performance for C-5 Network Processor Heat Sink (see January 21, 2002 — Preliminary Version • Printed ...
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AC Timing AC timing specifications consist of input requirements and output responses. The input Specifications requirements include setup and hold times, pulse widths, and high and low times. The output responses include delays from clock to signal. The AC timing ...
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HAPTER LECTRICAL PECIFICATIONS Figure 12 System Clock Timing Diagram Cycle 1 SCLK SCLKX CCLKn Table 37 System Clock Timing Description Min Symbol Parameter 1X Clk Mode 2X Clk Mode ...
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Unused clocks should be pulled to a known state (ground) through a resistor. If you are using a clock generator, disabling the output should not cause a tristate does, then the line should be pulled down. CP Timing ...
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HAPTER LECTRICAL PECIFICATIONS DS1/DS3 Timing Specifications The DS1/DS3 interface timing is shown in Figure 13 DS1/DS3 Ethernet Timing Diagram Cycle 1 CPn_0 (TCLK) CPn_2/3 (Tx) CPn_1 (RCLK) CPn_4/5 (Rx) Table 38 DS1/DS3 Ethernet Timing Description ...
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Ethernet Timing Specifications The 10/100 Ethernet interface timing is shown in Figure 14 10/100 Ethernet Timing Diagram Cycle 1 CPn_0 (TCLK) CPn_2/3/6 (Tx) CPn_1/4/5 (Rx) Table 39 10/100 Ethernet Timing Description Symbol Parameter Tcet Tceo Tces Tceh * STD/Fast ...
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HAPTER LECTRICAL PECIFICATIONS Gigabit GMII Ethernet, TBI and MII Interface Timing Specifications The Gigabit GMII Ethernet interface timing is shown in Table Figure 15 Gigabit Ethernet and TBI Interface Timing Diagram GMII / TBI Tx ...
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Table 40 Gigabit GMII/MII Ethernet Interface Timing Description Symbol Gigabit Parameter Tcgt Tcgo Tcgr Tcgs Tcgh Tcmt Tcmo Table 41 Gigabit TBI Interface Timing Description Symbol TBI Tctt Tcto Tctr Tctd Tcts Tcth * For Fibre Channel applications this value ...
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HAPTER LECTRICAL PECIFICATIONS OC-3 Timing Specifications The OC-3 interface timing is shown in Figure 16 OC-3 Timing Diagram Cycle 2 Cycle 1 CPn_2 T CPn_3 Cycle 1 CPn_0 CPn_1 T c3r T c3d CPn_4 CPn_5 ...
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OC-12 Timing Specifications The OC-12 interface timing is shown in Figure 17 OC-12 Timing Diagram Cycle 1 CPn_1 (TCLKI) T c12d CPn_0 (TCLK) CPn_2-6 (Tx) Cycle 1 CPn_1 (RCLK) T c12r CPn_2-6 (Rx) Table 43 OC-12 Timing Description Symbol Parameter ...
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HAPTER LECTRICAL PECIFICATIONS Executive Processor The XP timing specifications include: Timing Specifications • • • • PCI Timing Specifications The PCI timing is shown in Figure 18 PCI Timing Diagram Cycle 1 PCLK PAD/P_ctl (output) ...
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Table 44 PCI Timing Description Symbol Parameter Tpc Tpas Tpah Tpao Tpaz Tpav Tpgs Tpgh Tpis Tpih * 66MHz PCI † P_ctl includes all PCI control parameters including: PPAR, PFRAMEX, PTRDYX, PIRDYX, PSTOPX, PDEVSELX, PPERRX, PSERRX ‡ Not fully tested, ...
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HAPTER LECTRICAL PECIFICATIONS MDIO Serial Interface Timing Specifications The MDIO serial interface timing is shown in Figure 19 MDIO Serial Interface Timing Diagram Cycle 2 SICL T SIDA (output) SIDA (input) Table 45 MDIO Serial ...
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Low Speed Serial Interface Timing Specifications The low speed serial interface timing is shown in Figure 20 Low Speed Serial Interface Timing Diagram Cycle 2 SICL T T su:s hd:s SIDA Table 46 Low Speed Serial Interface Timing Description Symbol ...
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HAPTER LECTRICAL PECIFICATIONS PROM Interface Timing Specifications The PROM interface timing is shown in Figure 21 PROM Interface Timing Diagram Cycle 1 SPCK SPDI SPLD SPDO Table 47 PROM Interface Timing Description Symbol Parameter Tspc ...
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Fabric Processor Timing The FP timing specifications are shown in Specifications Figure 22 Fabric Processor Timing Diagram Cycle 1 FRXCLK FRXCTL (output) T frco FRXCTL (input) FINn FTXCLK FTXCTL (output) T ftco FTXCTL (input) FOUTn C-Port Confidential Cycle 2 Cycle ...
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HAPTER LECTRICAL PECIFICATIONS Table 48 Fabric Processor Timing Description Symbol Parameter Tfrc Tfrcs Tfrch Tfrco Tfrcz Tfrcv Tfrds Tfrdh Tftc Tftcs Tftch Tftco Tftcz Tftcv Tftdo * Not fully tested, values based on design/characterization. January ...
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BMU Timing The BMU timing specifications are shown in Specifications The BMU synchronous DRAM interface is PC100-compliant and designed to work with industry standard SDRAM components with 12 or fewer address lines. The information below is intended to provide the ...
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HAPTER LECTRICAL PECIFICATIONS Table 50 Signal Groups in BMU Timing Diagrams Signal Group Control (M_ctl) Address (MAn) Data (MDn) TLU Timing The TLU timing specifications are shown in Specifications Figure 24 TLU Timing Diagram Cycle ...
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Table 52 Signal Groups in TLU Timing Diagrams Signal Group Control (T_ctl) Address (TAn) Data (TDn) QMU Timing The QMU timing specifications are shown in Specifications Figure 25 QMU Timing Diagram Cycle 1 QCLK QCMDn (output) QDATAn (output) T qdo ...
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HAPTER LECTRICAL PECIFICATIONS Table 53 QMU Timing Description (continued) (continued) Symbol Parameter Tqdz Tqdv * Not fully tested, values based on design/characterization. Table 54 Signal Groups in QMU Timing Diagrams Signal Group QCMDn QDATAn January ...
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Chapter 4 Mechanical Specifications Package Views The C-5 network processor is an 838 pin (29 pins x 29 pins) Ball Grid Array (BGA) package as shown in the following illustrations. Figure 26 C-5 Network Processor BGA Package Side View HiTCE: ...
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HAPTER ECHANICAL PECIFICATIONS Figure 27 C-5 Network Processor BGA Package (Bottom View ...
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Package Table 55 Measurements maximum sizes where appropriate. Table 55 Package Measurements (Reference Symbol Marking Codes Table 56 Table 56 C-5 Network Processor Marking Codes Marking (Explanation of Codes) ...
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HAPTER ECHANICAL PECIFICATIONS Solder ball voiding may be affected by ramp rates and dwell times below and above liquidus nitrogen atmosphere is not required, but will make the process more robust. It can ...
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Index Symbols 10/100 Ethernet (RMII) Configuration 26 10/100 Ethernet Signals 27 10/100 Ethernet Timing Description 73 10/100 Ethernet Timing Diagram 73 10/100 Ethernet Timing Specifications 73 A About This Guide 11 Absolute Maximum Ratings 63 AC Timing Specifications 69 B ...
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NDEX Gigabit Ethernet (TBI) Timing 74 Low Speed Serial Interface Timing 81 MDIO Serial Interface Timing 80 OC-3 Timing 76 PCI Timing 78 Pinout 22 PROM Interface 36 PROM Interface Timing 82 QMU Timing 87 Signal ...
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N No Connection Pins 48 O OC-12 Signals 32 OC-12 Timing Description 77 OC-12 Timing Specifications 77 OC-3 Signals 31 OC-3 Timing Description 76 OC-3 Timing Diagram 76 OC-3 Timing Specifications 76 Operating Conditions, Recommended 64 P Package Measurements 91 ...
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NDEX CP Timing 71 DS1/DS3 Timing 72 Electrical 63 Executive Processor Timing 78 Fabric Processor Timing 83 Gigabit GMII Ethernet, TBI and MII Interface Timing Specification 74 Low Speed Serial Interface Timing 81 MDIO Serial Interface ...
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Part Number: 4-004 C-Port Corporation 120 Water Street North Andover, MA 01845 978-773-2300 TEL 978-773-2301 FAX www.cportcorp.com www.mot-sps.com ...