MCC501RX166TD0B Motorola / Freescale Semiconductor, MCC501RX166TD0B Datasheet - Page 36

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MCC501RX166TD0B

Manufacturer Part Number
MCC501RX166TD0B
Description
Network Processor, 16 Processing Elements, 166MHz Core Operating Frequency, 5Gbps Max Throughput, 838-CBGA
Manufacturer
Motorola / Freescale Semiconductor
Datasheet
36
January 21, 2002— Preliminary Version
C
HAPTER
2: S
IGNAL
D
ESCRIPTIONS
Figure 4 PROM Interface Diagram
The PROM interface operates in the following manner (Note that two accesses are
piplined together to execute one 32-bit fetch). The steps are shown in
1 The PROM_ADDR is loaded into the network processor internal shift register.
2 The PROM_ADDR is shifted into the external shift register for 22 SPCLK cycles.
3 SPLD is asserted for one SPCLK cycle, loading the PROM_ADDR into the external
4 SPLD is deasserted for 22 SPCLK cycles. The PROM presents the first 16bit
5 SPLD is asserted for one SPCLK cycle, loading the PROM_ADDR into the external
6 SPLD is deasserted for 22 SPCLK cycles, shifting the first PROM_DATA into the network
7 SPLD is asserted for one SPCLK cycle, loading the first PROM_DATA into the network
presentation register.
PROM_DATA. At the same time, the next PROM_ADDR is shifted into the external shift
register.
presentation register and the first PROM_DATA into the external shift register.
processor internal shift register.
processor PROM_RETURN_DATA register and the second PROM_DATA into the
external shift register.
PROM _Return_Data
31
PROM _H_Word
21
21
PROM_ADDR<21:1>
16
C-5 Network Processor
15
15
PROM _LO_Word
PROM Clock Gen.
PROM Sequencer
21
Internal Shift
6
Register
CE
0
0
1
0
SPCLK
SPLD
SPDO
External Logic
SPDI
PROM_ADDR<21:1>
21
21
21
External Shift
PROM
Register
6 0
CE
0
1
Figure
PROM_Data
16
C-Port Confidential
5.

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