MCC501RX166TD0B Motorola / Freescale Semiconductor, MCC501RX166TD0B Datasheet - Page 35

• Manufacturer Part Number: MCC501RX166TD0B
• Description: Network Processor, 16 Processing Elements, 166MHz Core Operating Frequency, 5Gbps Max Throughput, 838-CBGA
• Manufacturer: Motorola / Freescale Semiconductor

C-Port Confidential
of the devices connected to the bus must have either an open-drain or open-collector in
order to perform the wired-AND function required for its arbitration mechanism.
Table 13 Serial Port Signals
PROM Interface Signals
The PROM interface is a low speed I/O port that allows the C-5 NP to communicate
through external logic to PROM. The PROM clock is
maximum PROM size is 4MBytes x 16, and configuration is required. The PROM signals are
listed in
Table 14 PROM Interface Signals
Figure 4
The application is required to provide an external shift register with parallel-in and
parallel-out capabilities, and a parallel load register. Both devices should be
positive-edge-triggered and perform a parallel load whenever SPLD is asserted. When
SPLD is deasserted the shift register shifts.
Signal Name
SICL
SIDA
Total Pins
Signal
Name
SPDO
SPDI
SPLD
SPCK
Total Pins
Table 14
shows the connections between the PROM Interface and external board logic.
Pin #
N15
N16
M16
M14
.
Pin #
O14
N14
Total Type
1
1
1
1
4
Total Type
1
1
2
LVTTL
LVTTL
LVTTL
LVTTL
LVTTL
LVTTL
I/O
O
I
O
O
Signal Description
Serial Data Out
Serial Data In
When load is asserted on a positive clock
edge, the external logic performs a parallel
load. On each positive clock edge when
load is de-asserted, the shift registers shift.
When the PROM interface is idle:
•
•
Clock
Pin Descriptions Grouped by Function
I/O
I/O
I/O
if SPLD is asserted HI it indicates low
speed serial protocol,
if asserted LOW it indicates MDIO serial
protocol.
1
/
2
Signal Description
Serial Clock line
Serial Data line
to
1
/
16
Preliminary Version — January 21, 2002
the core clock rate. The
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