ST72324BJ4-auto STMicroelectronics, ST72324BJ4-auto Datasheet - Page 99

• Manufacturer Part Number: ST72324BJ4-auto
• Description: 8-bit MCU for automotive, 3.8 to 5.5V operating range with 16 Kbyte Flash, 10-bit ADC, 4 timers, SPI, SCI
• Manufacturer: STMicroelectronics

Specifications of ST72324BJ4-auto

• Hdflash Endurance: 100 cycles, data retention 20 years
• Clock Sources: crystal/ceramic resonator oscillators, internal RC oscillator and external clock input
• 4 Power Saving Modes: Slow, Wait, Active Halt, and Halt

ST72324B-Auto
The MOSI pins are connected together and the MISO pins are connected together. In this
way data is transferred serially between master and slave (most significant bit first).
The communication is always initiated by the master. When the master device transmits
data to a slave device via MOSI pin, the slave device responds by sending data to the
master device via the MISO pin. This implies full duplex communication with both data out
and data in synchronized with the same clock signal (which is provided by the master device
via the SCK pin).
To use a single data line, the MISO and MOSI pins must be connected at each node (in this
case only simplex communication is possible).
Four possible data/clock timing relationships may be chosen (see
slave must be programmed with the same timing mode.
Figure 49. Single master/single slave application
Slave Select management
As an alternative to using the SS pin to control the Slave Select signal, the application can
choose to manage the Slave Select signal by software. This is configured by the SSM bit in
the SPICSR register (see
In software management, the external SS pin is free for other application uses and the
internal SS signal level is driven by writing to the SSI bit in the SPICSR register.
In Master mode:
●
Depending on the data/clock timing relationship, there are two cases in Slave mode (see
Figure
If CPHA = 1 (data latched on second clock edge):
●
If CPHA = 0 (data latched on first clock edge):
●
SS internal must be held high continuously
SS internal must be held low during the entire transmission. This implies that in single
slave applications the SS pin either can be tied to V
managing the SS function by software (SSM = 1 and SSI = 0 in the in the SPICSR
register)
SS internal must be held low during byte transmission and pulled high between each
byte to allow the slave to write to the shift register. If SS is not pulled high, a Write
50):
MSB
generator
clock
8-bit Shift Register
SPI
Master
Figure
LSB
Doc ID13466 Rev 4
51).
MOSI
SCK
SS
MISO
+5V
MISO
MOSI
SCK
SS
SS
, or made free for standard I/O by
MSB
Not used if SS is managed
by software
Figure
8-bit Shift Register
On-chip peripherals
Slave
52) but master and
LSB
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