ST72324BJ4-auto STMicroelectronics, ST72324BJ4-auto Datasheet - Page 125

• Manufacturer Part Number: ST72324BJ4-auto
• Description: 8-bit MCU for automotive, 3.8 to 5.5V operating range with 16 Kbyte Flash, 10-bit ADC, 4 timers, SPI, SCI
• Manufacturer: STMicroelectronics

Specifications of ST72324BJ4-auto

• Hdflash Endurance: 100 cycles, data retention 20 years
• Clock Sources: crystal/ceramic resonator oscillators, internal RC oscillator and external clock input
• 4 Power Saving Modes: Slow, Wait, Active Halt, and Halt

ST72324B-Auto
Table 63.
SCI Control Register 2 (SCICR2)
Table 64.
SCICR2
Bit
Bit
7
6
3
2
1
0
R/W
TIE
7
WAKE
Name
Name
TCIE
PCE
PIE
TIE
PS
SCICR1 register description (continued)
SCICR2 register description
Wake-Up method
Parity Control Enable
Parity Selection
Parity Interrupt Enable
Transmitter Interrupt Enable
Transmission Complete Interrupt Enable
TCIE
R/W
This bit determines the SCI Wake-Up method, it is set or cleared by software.
0: Idle line
1: Address mark
This bit selects the hardware parity control (generation and detection). When the
parity control is enabled, the computed parity is inserted at the MSB position (9th bit
if M = 1; 8th bit if M = 0) and parity is checked on the received data. This bit is set
and cleared by software. Once it is set, PCE is active after the current byte (in
reception and in transmission).
0: Parity control disabled
1: Parity control enabled
This bit selects the odd or even parity when the parity generation/detection is
enabled (PCE bit set). It is set and cleared by software. The parity will be selected
after the current byte.
0: Even parity
1: Odd parity
This bit enables the interrupt capability of the hardware parity control when a parity
error is detected (PE bit set). It is set and cleared by software.
0: Parity error interrupt disabled
1: Parity error interrupt enabled
This bit is set and cleared by software.
0: Interrupt is inhibited
1: An SCI interrupt is generated whenever TDRE = 1 in the SCISR register.
This bit is set and cleared by software.
0: Interrupt is inhibited
1: An SCI interrupt is generated whenever TC = 1 in the SCISR register.
6
R/W
RIE
5
Doc ID13466 Rev 4
R/W
ILIE
4
Function
Function
R/W
TE
3
R/W
RE
2
Reset value: 0000 0000 (00h)
On-chip peripherals
RWU
R/W
1
SBK
R/W
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