ST72324BJ4-auto STMicroelectronics, ST72324BJ4-auto Datasheet
ST72324BJ4-auto
Specifications of ST72324BJ4-auto
Related parts for ST72324BJ4-auto
ST72324BJ4-auto Summary of contents
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... Table 1. Device summary Device Memory ST72324BK2-Auto Flash/ROM 8 Kbytes ST72324BK4-Auto Flash/ROM 16 Kbytes ST72324BK6-Auto Flash/ROM 32 Kbytes ST72324BJ2-Auto Flash/ROM 8 Kbytes ST72324BJ4-Auto Flash/ROM 16 Kbytes ST72324BJ6-Auto Flash/ROM 32 Kbytes July 2010 ST72324Bxx-Auto LQFP44 timers ■ Main clock controller with Real-time base, Beep and Clock-out capabilities ■ ...
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Contents Contents 1 Description . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . ...
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ST72324B-Auto 6.3.3 6.4 Reset sequence manager (RSM 6.4.1 ...
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Contents 9.1 Introduction . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . ...
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ST72324B-Auto 10.3.7 10.4 Serial peripheral interface (SPI ...
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Contents 12 Electrical characteristics . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 145 ...
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ST72324B-Auto 12.10 Control pin characteristics . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . ...
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Contents 15.1.3 15.1.4 15.1.5 15.1.6 15.1.7 15.2 8/16 Kbyte Flash devices only . . . . . . . . . . . . . . . . . . . . . . . . . . . . ...
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ST72324B-Auto List of tables Table 1. Device summary . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . ...
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List of tables Table 49. CR1 register description . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . ...
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... Table 117. Option byte 0 bit description . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 179 Table 118. Option byte 1 bit description . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 180 Table 119. Package selection (OPT7 181 Table 120. STMicroelectronics development tools . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 188 Table 121. Suggested list of socket types . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 188 Table 122. Port A and F configuration . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 194 Table 123. Document revision history . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 195 ...
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List of figures List of figures Figure 1. Device block diagram . . . . . . . . . . . . . . . . . . . . . . . . . . . . . ...
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ST72324B-Auto Figure 49. Single master/single slave application . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . ...
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Description 1 Description The ST72324B-Auto devices are members of the ST7 microcontroller family designed for mid-range automotive applications running from 3.8 to 5.5V. Different package options offer I/O pins. All devices are based on a common industry-standard ...
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ST72324B-Auto 2 Pin description Figure 2. 44-pin LQFP package pinout Figure 3. 32-pin LQFP package pinout See Section 12: Electrical characteristics on page 145 guidelines RDI / PE1 1 ...
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Pin description Refer to Section 9: I/O ports on page 58 I/O ports. The reset configuration of each pin is shown in bold. This configuration is valid as long as the device is in reset state. Table 2. Device pin ...
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ST72324B-Auto Table 2. Device pin description (continued) Pin No. Name PC3 I/O C (HS)/ICAP1_B PC4/MISO/ICCD 27 12 I/O C ATA PC5/MOSI I/O C /AIN14 PC6/SCK I/O C /ICCCLK 30 15 PC7/SS/AIN15 I/O C ...
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Pin description Table 2. Device pin description (continued) Pin No. Name 2 28 PB0 I PB1 I PB2 I PB3 I mandatory to connect all available V ...
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ST72324B-Auto 3 Register and memory map As shown in Figure 4 registers. The available memory locations consist of 128 bytes of register locations 1024 bytes of RAM and Kbytes of user program memory. The RAM ...
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Register and memory map Table 3. Hardware register map (continued) Address Block Register label 000Fh PFDR (1) 0010h Port F PFDDR 0011h PFOR 0012h to 0020h 0021h SPIDR 0022h SPI SPICR 0023h SPICSR 0024h ISPR0 0025h ISPR1 0026h ISPR2 ITC ...
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ST72324B-Auto Table 3. Hardware register map (continued) Address Block Register label 0041h TBCR2 0042h TBCR1 0043h TBCSR 0044h TBIC1HR 0045h TBIC1LR 0046h TBOC1HR 0047h TBOC1LR 0048h Timer B TBCHR 0049h TBCLR 004Ah TBACHR 004Bh TBACLR 004Ch TBIC2HR 004Dh TBIC2LR 004Eh ...
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Flash program memory 4 Flash program memory 4.1 Introduction The ST7 dual voltage High Density Flash (HDFlash non-volatile memory that can be electrically erased as a single block or by individual sectors and programmed on a byte-by- byte ...
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ST72324B-Auto 4.3.1 Readout protection Readout protection, when selected, provides a protection against program memory content extraction and against write access to Flash memory. Even if no protection can be considered as totally unbreakable, the feature provides a very high level ...
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... Depending on the ICP code downloaded in RAM, Flash memory programming can be fully customized (number of bytes to program, program locations, or selection serial communication interface for downloading). When using an STMicroelectronics or third-party programming tool that supports ICP and the specific microcontroller device, the user needs only to implement the ICP hardware interface on the application board (see to the device pinout description ...
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ST72324B-Auto 4.6 IAP (in-application programming) This mode uses a BootLoader program previously stored in Sector 0 by the user (in ICP mode or by plugging the device in a programming tool). This mode is fully controlled by user software. This ...
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Central processing unit (CPU) 5 Central processing unit (CPU) 5.1 Introduction This CPU has a full 8-bit architecture and contains six internal registers allowing efficient 8- bit data manipulation. 5.2 Main features ● Enable executing 63 basic instructions ● Fast ...
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ST72324B-Auto 5.3.1 Accumulator (A) The Accumulator is an 8-bit general purpose register used to hold operands and the results of the arithmetic and logic calculations and to manipulate data. 5.3.2 Index registers (X and Y) These 8-bit registers are used ...
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Central processing unit (CPU) Table 6. Arithmetic management bits (continued) BIt Name Zero (Arithmetic Management bit) This bit is set and cleared by hardware. This bit indicates that the result of the last arithmetic, logical or data manipulation is zero. ...
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ST72324B-Auto 5.3.5 Stack Pointer register (SP R/W R/W R/W R/W R/W R/W R/W R/W R/W R/W R/W R/W R/W R/W R/W R/W The Stack Pointer is a 16-bit register which is always pointing ...
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Central processing unit (CPU) Figure 8. Stack manipulation example Call subroutine @ 0100h SP PCH PCL @ 01FFh Stack Higher Address = 01FFh Stack Lower Address = 0100h 30/198 Push Y Interrupt event ...
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ST72324B-Auto 6 Supply, reset and clock management 6.1 Introduction The device includes a range of utility features for securing the application in critical situations (for example in case of a power brown-out), and reducing the number of external components. An ...
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Supply, reset and clock management Figure 10. Clock, reset and supply block diagram Multi- OSC2 Oscillator OSC1 (MO) Reset Sequence RESET Manager (RSM 6.3 Multi-oscillator (MO) The main clock of the ST7 can be generated by ...
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ST72324B-Auto 6.3.2 Crystal/ceramic oscillators This family of oscillators has the advantage of producing a very accurate rate on the main clock of the ST7. The selection within a list of four oscillators with different frequency ranges has to be done ...
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Supply, reset and clock management 6.4 Reset sequence manager (RSM) The reset sequence manager includes three reset sources as shown in ● External reset source pulse ● Internal LVD reset ● Internal Watchdog reset These sources act on the RESET ...
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ST72324B-Auto Figure 12. Reset block diagram RESET The RESET pin is an asynchronous signal which plays a major role in EMS performance noisy environment recommended to follow the guidelines mentioned in the electrical characteristics section. External ...
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Supply, reset and clock management Figure 13. RESET sequences IT+(LVD) V IT-(LVD) Run Active phase External RESET source RESET pin Watchdog reset 6.5 System integrity management (SI) The system integrity management block contains the LVD and auxiliary ...
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ST72324B-Auto Provided the minimum V MCU can only be in two modes: ● under full software control ● in static safe reset In these conditions, secure operation is always ensured for the application without the need for external reset hardware. ...
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Supply, reset and clock management The interrupt on the rising edge is used to inform the application that the V is over. If the voltage rise time t selected by option byte), no AVD interrupt will be generated when V ...
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ST72324B-Auto 6.6 SI registers 6.6.1 System integrity (SI) control/status register (SICSR) SICSR 7 6 Res AVDIE - R/W Table 12. SICSR register description Bit Name 7 - Reserved, must be kept cleared Voltage Detector Interrupt Enable This bit is set ...
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Supply, reset and clock management Application notes The LVDRF flag is not cleared when another reset type occurs (external or watchdog); the LVDRF flag remains set to keep trace of the original failure. In this case, a watchdog reset can ...
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ST72324B-Auto 7 Interrupts 7.1 Introduction The ST7 enhanced interrupt management provides the following features: ● Hardware interrupts ● Software interrupt (TRAP) ● Nested or concurrent interrupt management with flexible interrupt priority and level management: – software programmable ...
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Interrupts Table 14. Interrupt software priority levels Interrupt software priority Level 0 (main) Level 1 Level 2 Level 3 (= interrupt disable) Figure 16. Interrupt processing flowchart Reset RESTORE PC 7.2.1 Servicing pending interrupts As several interrupts ...
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ST72324B-Auto When an interrupt request is not serviced immediately latched and then processed when its software priority combined with the hardware priority becomes the highest one. Note: 1 The hardware priority is exclusive while the software one is ...
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Interrupts peripheral control register. The general sequence for clearing an interrupt is based on an access to the status register followed by a read or write to an associated register. Note: The clearing sequence resets the internal latch. A pending ...
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ST72324B-Auto Figure 19. Nested interrupt management RIM Main 7.5 Interrupt registers 7.5.1 CPU CC register interrupt bits CPU Table 15. CPU CC register interrupt bits description Bit Name ...
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Interrupts They can be also set/cleared by software with the RIM, SIM, HALT, WFI, IRET and PUSH/POP instructions (see 7.5.2 Interrupt software priority registers (ISPRx) ISPRx 7 ISPR0 I1_3 ISPR1 I1_7 ISPR2 I1_11 R/W ISPR3 1 RO These four registers ...
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ST72324B-Auto Table 18. Dedicated interrupt instruction set Instruction IRET Interrupt routine return JRM Jump if I1:0=11 (level 3) JRNM Jump if I1:0<>11 POP CC POP CC from the Stack RIM Enable interrupt (level 0 set) Load 10 in I1:0 of ...
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Interrupts 7.6 External interrupts 7.6.1 I/O port interrupt sensitivity The external interrupt sensitivity is controlled by the IPA, IPB and ISxx bits of the EICR register (Figure 20). This control allows up to four fully independent external interrupt source sensitivities. ...
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ST72324B-Auto 7.6.2 External interrupt control register (EICR) EICR 7 6 IS11 IS10 R/W R/W Table 19. EICR register description Bit Name ei2 and ei3 sensitivity The interrupt sensitivity, defined using the IS1[1:0] bits, is applied to the following external interrupts: ...
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Interrupts Table 21. Interrupt sensitivity - ei3 IS11 IS10 Table 22. Interrupt sensitivity - ei0 IS21 IS20 Table 23. Interrupt sensitivity - ei1 IS21 ...
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ST72324B-Auto Table 25. Interrupt mapping Source No. Description block Reset Reset TRAP Software interrupt 0 Main clock controller time base 1 MCC/RTC interrupt 2 ei0 External interrupt port A3..0 3 ei1 External interrupt port F2..0 4 ei2 External interrupt port ...
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Power saving modes 8 Power saving modes 8.1 Introduction To give a large measure of flexibility to the application in terms of power consumption, four main power saving modes are implemented in the ST7 (see Wait), Active Halt and Halt. ...
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ST72324B-Auto Figure 22. Slow mode clock transitions 8.3 Wait mode Wait mode places the MCU in a low power consumption mode by stopping the CPU. This power saving mode is selected by calling the ‘WFI’ instruction. All peripherals remain active. ...
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Power saving modes 8.4 Active Halt and Halt modes Active Halt and Halt modes are the two lowest power consumption modes of the MCU. They are both entered by executing the ‘HALT’ instruction. The decision to enter either in Active ...
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ST72324B-Auto Figure 25. Active Halt mode flowchart 1. Peripheral clocked with an external clock source can still be active. 2. Only the MCC/RTC interrupt and some specific interrupts can exit the MCU from Active Halt mode (such as external interrupt). ...
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Power saving modes Figure 26. HALT timing overview Figure 27. Halt mode flowchart 1. WDGHALT is an option bit. See 2. Peripheral clocked with an external clock source can still be active. 3. Only some specific interrupts can exit the ...
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ST72324B-Auto Halt mode recommendations ● Make sure that an external event is available to wake up the microcontroller from Halt mode. ● When using an external interrupt to wake up the microcontroller, reinitialize the corresponding I/O as “Input Pull-up with ...
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I/O ports 9 I/O ports 9.1 Introduction The I/O ports offer different functional modes: ● transfer of data through digital inputs and outputs, and for specific pins: ● external interrupt generation, ● alternate signal input/output for the on-chip peripherals. An ...
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ST72324B-Auto External interrupt function When an I/O is configured as ‘Input with Interrupt’, an event on this I/O can generate an external interrupt request to the CPU. Each pin can independently generate an interrupt request. The interrupt sensitivity is independently ...
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I/O ports Figure 28. I/O port general block diagram Register access DR DDR OR OR SEL DDR SEL DR SEL External interrupt source ( Table 28. I/O port mode options Configuration mode Floating with/without Interrupt Input Pull-up with/without ...
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ST72324B-Auto Table 29. I/O port configurations Not implemented in true open drain I/O ports Not implemented in true open drain I/O ports Pad Not implemented in true open drain I/O ports Pad 1. When the I/O port is in input ...
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I/O ports Analog alternate function When the pin is used as an ADC input, the I/O must be configured as floating input. The analog multiplexer (controlled by the ADC registers) switches the analog voltage present on the selected pin to ...
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ST72324B-Auto Table 31. I/O port interrupt control/wake-up capability Interrupt event External interrupt on selected external event 9.5.1 I/O port implementation The I/O port register configurations are summarized Table 32. Port configuration Port Pin name PA7:6 Port A PA5:4 PA3 PB3 ...
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I/O ports Table 33. I/O port register map and reset values (continued) Address (Hex.) 000Ch 000Dh 000Eh 000Fh 0010h 0011h 64/198 Register label 7 6 PEDR PEDDR MSB PEOR PFDR PFDDR MSB PFOR Doc ID13466 Rev 4 ST72324B-Auto 5 4 ...
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ST72324B-Auto 10 On-chip peripherals 10.1 Watchdog timer (WDG) 10.1.1 Introduction The Watchdog timer is used to detect the occurrence of a software fault, usually generated by external interference or by unforeseen logical conditions, which causes the application program to abandon ...
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On-chip peripherals Figure 30. Watchdog block diagram MCC/RTC 12-bit MCC RTC counter MSB 11 10.1.4 How to program the Watchdog timeout Figure 31 shows the linear relationship between the 6-bit value to be loaded in the Watchdog Counter (CNT) and ...
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ST72324B-Auto Figure 32. Exact timeout duration (t : WHERE t = (LSB + 128 min0 t = 16384 x t max0 OSC2 t = 125ns if f OSC2 OSC2 CNT = value of T[5:0] bits in ...
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On-chip peripherals 10.1.5 Low power modes Table 34. Effect of lower power modes on Watchdog Mode Slow No effect on Watchdog Wait OIE bit in MCCSR register 0 Halt 0 1 10.1.6 Hardware Watchdog option If Hardware Watchdog is selected ...
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ST72324B-Auto 10.1.9 Control register (WDGCR) WDGCR 7 6 WDGA R/W Table 35. WDGCR register description Bit Name Activation bit This bit is set by software and only cleared by hardware after a reset. When WDGA = 1, the watchdog can ...
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On-chip peripherals 10.2.2 Clock-out capability The clock-out capability is an alternate function of an I/O port pin that outputs the f to drive external devices controlled by the MCO bit in the MCCSR register. Caution: When selected, the ...
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ST72324B-Auto 10.2.5 Low power modes Table 37. Effect of low power modes on MCC/RTC Mode Wait Active Halt Halt 10.2.6 Interrupts The MCC/RTC interrupt event generates an interrupt if the OIE bit of the MCCSR register is set and the ...
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On-chip peripherals Table 39. MCCSR register description (continued) Bit Name CPU Clock Prescaler These bits select the CPU clock prescaler which is applied in different slow modes. Their action is conditioned by the setting of the SMS bit. These two ...
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ST72324B-Auto MCC beep control register (MCCBCR) MCCBCR 7 6 Table 41. MCCBCR register description Bit Name 7:2 - Reserved, must be kept cleared Beep Control These 2 bits select the PF1 pin beep capability (see 1:0 BC[1:0] signal is available ...
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On-chip peripherals 10.3 16-bit timer 10.3.1 Introduction The timer consists of a 16-bit free-running counter driven by a programmable prescaler. It may be used for a variety of purposes, including pulse length measurement two input signals (input ...
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ST72324B-Auto 10.3.3 Functional description Counter The main block of the programmable timer is a 16-bit free running upcounter and its associated 16-bit registers. The 16-bit registers are made up of two 8-bit registers called high and low. ● Counter Register ...
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On-chip peripherals Figure 34. Timer block diagram fCPU EXEDG 1/2 1/4 1/8 EXTCLK pin CC[1:0] ICF1 OCF1 TOF ICIE OCIE TOIE (See note 1) Timer interrupt 1. If IC, OC and TO interrupt requests have separate vectors then the last ...
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ST72324B-Auto 16-bit read sequence The 16-bit read sequence (from either the Counter register or the Alternate Counter register) is illustrated in the 16-bit read sequence Figure 35. The user must first read the MSB, afterwhich the LSB value is automatically ...
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On-chip peripherals External clock The external clock (where available) is selected if CC0 = 1 and CC1 = 1 in the CR2 register. The status of the EXEDG bit in the CR2 register determines the type of level transition on ...
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ST72324B-Auto Input capture In this section, the index, i, may because there are two input capture functions in the 16-bit timer. The two 16-bit input capture registers (IC1R/IC2R) are used to latch the value of the ...
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On-chip peripherals Note: 1 After reading the ICiHR register, transfer of input capture data is inhibited and ICFi will never be set until the ICiLR register is also read. 2 The ICiR register contains the free running counter value which ...
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ST72324B-Auto Output compare In this section, the index, i, may because there are two output compare functions in the 16-bit timer. This function can be used to control an output waveform or indicate when a period ...
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On-chip peripherals If the timer clock is an external clock, the formula is: Where: t = Output compare period (in seconds) External timer clock frequency (in hertz) EXT Clearing the output compare interrupt request (that is, clearing the ...
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ST72324B-Auto Figure 41. Output compare block diagram 16-bit free running counter 16-bit Output compare 16-bit 16-bit OC1R register OC2R register Figure 42. Output compare timing diagram, f Output Compare register i (OCRi) Figure 43. Output compare timing diagram, f Output ...
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On-chip peripherals One Pulse mode One Pulse mode enables the generation of a pulse when an external event occurs. This mode is selected via the OPM bit in the CR2 register. The one pulse mode uses the Input Capture1 function ...
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ST72324B-Auto The OC1R register value required for a specific timing application can be calculated using the following formula: Where Pulse period (in seconds) CPU clock frequnency (in hertz) CPU PRESC = Timer prescaler factor (2, 4 ...
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On-chip peripherals Figure 46. Pulse width modulation mode timing example with two output compare functions Counter 34E2 OCMP1 1. OC1R = 2ED0h, OC2R = 34E2, OLVL1 = 0, OLVL2 = timers with only one Output Compare register, ...
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ST72324B-Auto Figure 47. Pulse width modulation cycle If OLVL1 = 1 and OLVL2 = 0, the length of the positive pulse is the difference between the OC2R and OC1R registers. If OLVL1 = OLVL2, a continuous signal will be seen ...
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On-chip peripherals 10.3.4 Low power modes Table 46. Effect of low power modes on 16-bit timer Mode No effect on 16-bit timer. Wait Timer interrupts cause the device to exit from Wait mode. 16-bit timer registers are frozen. In Halt ...
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ST72324B-Auto 10.3.6 Summary of timer modes Table 48. Summary of timer modes Mode Input Capture (1 and/or 2) Output Compare (1 and/or 2) One Pulse mode PWM mode 1. See note 4 in One Pulse mode on page 2. See ...
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On-chip peripherals Table 49. CR1 register description (continued) Bit Name Forced Output compare 2 This bit is set and cleared by software. 4 FOLV2 0: No effect on the OCMP2 pin. 1: Forces the OLVL2 bit to be copied to ...
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ST72324B-Auto M Table 50. CR2 register description Bit Name Output Compare 1 Pin Enable This bit is used only to output the signal from the timer on the OCMP1 pin (OLV1 in Output Compare mode, both OLV1 and OLV2 in ...
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On-chip peripherals Control/Status Register (CSR) CSR 7 6 ICF1 OCF1 Table 51. CSR register description Bit Name Input Capture Flag Input Capture (reset value). 7 ICF1 1: An Input Capture has occurred on the ...
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ST72324B-Auto Input Capture 1 High Register (IC1HR) This is an 8-bit register that contains the high part of the counter value (transferred by the input capture 1 event). IC1HR 7 6 MSB ...
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On-chip peripherals Input Capture 1 Low Register (IC1LR) This is an 8-bit register that contains the low part of the counter value (transferred by the input capture 1 event). IC1LR 7 6 MSB RO RO Output Compare 1 High Register ...
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ST72324B-Auto Output Compare 2 Low Register (OC2LR) This is an 8-bit register that contains the low part of the value to be compared to the CLR register. OC2LR 7 6 MSB R/W R/W Counter High Register (CHR) This is an ...
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On-chip peripherals Alternate Counter Low Register (ACLR) This is an 8-bit register that contains the low part of the counter value. A write to this register resets the counter. An access to this register after an access to CSR register ...
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ST72324B-Auto Table 52. 16-bit timer register map and reset values (continued) Address Register (Hex.) label Timer A: 35 IC1LR Timer B: 45 Reset value Timer A: 36 OC1HR Timer B: 46 Reset value Timer A: 37 OC1LR Timer B: 47 ...
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On-chip peripherals Note: In slave mode, continuous transmission is not possible at maximum frequency due to the software overhead for clearing status flags and to initiate the next transmission sequence. 10.4.3 General description Figure 49 shows the serial peripheral interface ...
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ST72324B-Auto The MOSI pins are connected together and the MISO pins are connected together. In this way data is transferred serially between master and slave (most significant bit first). The communication is always initiated by the master. When the master ...
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On-chip peripherals Collision error will occur when the slave writes to the shift register error (WCOL) on page Figure 50. Generic SS timing diagram MOSI/MISO Master SS Slave SS (if CPHA=0) Slave SS (if CPHA=1) Figure 51. Hardware/software slave select ...
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ST72324B-Auto Master mode transmit sequence When software writes to the SPIDR register, the data byte is loaded into the 8-bit shift register and then shifted out serially to the MOSI pin most significant bit first. When data transfer is complete: ...
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On-chip peripherals The SPIF bit can be cleared during a second transmission; however, it must be cleared before the second SPIF bit in order to prevent an Overrun condition (see (OVR) on page 103). 10.4.4 Clock phase and clock polarity ...
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ST72324B-Auto 10.4.5 Error flags Master mode fault (MODF) Master mode fault occurs when the master device has its SS pin pulled low. When a Master mode fault occurs: ● The MODF bit is set and an SPI interrupt request is ...
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On-chip peripherals Figure 53. Clearing the WCOL bit (Write Collision flag) software sequence Clearing sequence after SPIF = 1 (end of a data byte transfer) 1st Step Read SPICSR 2nd Step Clearing sequence before SPIF = 1 (during a data ...
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ST72324B-Auto 10.4.6 Low power modes Table 53. Effect of low power modes on SPI Mode No effect on SPI. Wait SPI interrupt events cause the device to exit from Wait mode. SPI registers are frozen. In Halt mode, ...
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On-chip peripherals 10.4.8 SPI registers SPI Control Register (SPICR) SPICR 7 6 SPIE SPE R/W R/W Table 55. SPICR register description Bit Name Serial Peripheral Interrupt Enable 7 SPIE Serial Peripheral Output Enable 6 SPE Divider Enable 5 SPR2 Master ...
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ST72324B-Auto Table 55. SPICR register description (continued) Bit Name Clock Phase 2 CPHA Serial clock frequency 1:0 SPR[1:0] Table 56. SPI master mode SCK frequency Serial clock f SPI Control/Status Register (SPICSR) SPICSR 7 6 SPIF WCOL RO RO This ...
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On-chip peripherals Table 57. SPICSR register description Bit Name Serial Peripheral data transfer flag This bit is set by hardware when a transfer has been completed. An interrupt is generated if SPIE = 1 in the SPICR register ...
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ST72324B-Auto SPI Data I/O Register (SPIDR) SPIDR R/W R/W The SPIDR register is used to transmit and receive data on the serial bus master device, a write to this register will initiate transmission/reception of ...
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On-chip peripherals 10.5 Serial communications interface (SCI) 10.5.1 Introduction The serial communications interface (SCI) offers a flexible means of full-duplex data exchange with external equipment requiring an industry standard NRZ asynchronous serial data format. The SCI offers a very wide ...
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ST72324B-Auto 10.5.3 General description The interface is externally connected to another device by two pins (see ● TDO: Transmit Data Output. When the transmitter and the receiver are disabled, the output pin returns to its I/O port configuration. When the ...
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On-chip peripherals Figure 55. SCI block diagram Write Transmit Data Register (TDR) TDO Transmit Shift Register RDI Transmit control CR2 TIE TCIE RIE SCI Interrupt control Transmitter clock f CPU 112/198 Read Received Data Register (RDR) Received Shift Register R8 ...
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ST72324B-Auto 10.5.4 Functional description The block diagram of the serial control interface is shown in dedicated registers: ● 2 control registers (SCICR1 and SCICR2) ● a status register (SCISR) ● a baud rate register (SCIBRR) ● an extended prescaler receiver ...
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On-chip peripherals Transmitter The transmitter can send data words of either bits depending on the M bit status. When the M bit is set, word length is 9 bits and the 9th bit (the MSB) has to ...
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ST72324B-Auto Break characters Setting the SBK bit loads the shift register with a break character. The break frame length depends on the M bit (see As long as the SBK bit is set, the SCI send break frames to the ...
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On-chip peripherals Overrun error An overrun error occurs when a character is received when RDRF has not been reset. Data can not be transferred from the shift register to the RDR register as long as the RDRF bit is not ...
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ST72324B-Auto Figure 57. SCI baud rate and extended prescaler block diagram f CPU /16 /PR Framing error A framing error is detected when: ● The stop bit is not recognized on reception at the expected time, following either a de- ...
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On-chip peripherals Conventional baud rate generation The baud rate for the receiver and transmitter (Rx and Tx) are set independently and calculated as follows: with (see SCP[1:0] bits ...
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ST72324B-Auto Receiver muting and wake-up feature In multiprocessor configurations it is often desirable that only the intended message recipient should actively receive the full message contents, thus reducing redundant SCI service overhead for all non-addressed receivers. The non-addressed devices may ...
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On-chip peripherals Even parity The parity bit is calculated to obtain an even number of ‘1’s inside the frame made of the LSB bits (depending on whether M is equal and the parity ...
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ST72324B-Auto Clock deviation causes The causes which contribute to the total deviation are: ● Deviation due to transmitter error (local oscillator error of the transmitter or the TRA transmitter is transmitting at a different baud rate). ● D ...
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On-chip peripherals 10.5.5 Low power modes Table 60. Effect of low power modes on SCI Mode No effect on SCI. Wait SCI interrupts cause the device to exit from Wait mode. SCI registers are frozen. Halt In Halt mode, the ...
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ST72324B-Auto Table 62. SCISR register description Bit Name Transmit Data Register Empty This bit is set by hardware when the content of the TDR register has been transferred into the shift register. An interrupt is generated if the TIE bit ...
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On-chip peripherals Table 62. SCISR register description (continued) Bit Name Framing Error This bit is set by hardware when a desynchronization, excessive noise or a break character is detected cleared by a software sequence (an access to the ...
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ST72324B-Auto Table 63. SCICR1 register description (continued) Bit Name Wake-Up method This bit determines the SCI Wake-Up method set or cleared by software. 3 WAKE 0: Idle line 1: Address mark Parity Control Enable This bit selects the ...
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On-chip peripherals Table 64. SCICR2 register description (continued) Bit Name Receiver interrupt Enable This bit is set and cleared by software. 5 RIE 0: Interrupt is inhibited SCI interrupt is generated whenever RDRF = ...
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ST72324B-Auto SCI Data Register (SCIDR) This register contains the received or transmitted data character, depending on whether it is read from or written to. SCIDR 7 6 DR7 DR6 R/W R/W The Data register performs a double function (read and ...
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On-chip peripherals Table 65. SCIBRR register description (continued) Bit Name SCI Transmitter rate divisor 5:3 SCT[2:0] SCI Receiver rate divisor 2:0 SCR[2:0] SCI Extended Receive Prescaler Division Register (SCIERPR) This register is used to set the Extended Prescaler rate division ...
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ST72324B-Auto SCIETPR 7 6 Table 67. SCIETPR register description Bit Name 7:0 ETPR[7:0] Table 68. Baud rate selection Symbol Parameter f CPU f Communication MHz f frequency ETPR[7:0] R/W 8-bit Extended Transmit Prescaler Register The ...
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On-chip peripherals Table 69. SCI register map and reset values Address (Hex.) Register label SCISR 0050h Reset value SCIDR 0051h Reset value SCIBRR 0052h Reset value SCICR1 0053h Reset value SCICR2 0054h Reset value SCIERPR 0055h Reset value SCIPETPR 0057h ...
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ST72324B-Auto 10.6 10-bit A/D converter (ADC) 10.6.1 Introduction The on-chip analog-to-digital converter (ADC) peripheral is a 10-bit, successive approximation converter with internal sample and hold circuitry. This peripheral has multiplexed analog input channels (refer to device pin ...
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On-chip peripherals 10.6.3 Functional description The conversion is monotonic, meaning that the result never decreases if the analog input does not increase. If the input voltage (V conversion result is FFh in the ADCDRH register and 03h in the ADCDRL ...
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ST72324B-Auto Changing the conversion channel The application can change channels during conversion. When software modifies the CH[3:0] bits in the ADCCSR register, the current conversion is stopped, the EOC bit is cleared, and the A/D converter starts converting the newly ...
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On-chip peripherals Table 71. ADCCSR register description Bit Name A/D Converter on This bit is set and cleared by software. 5 ADON 0: Disable ADC and stop conversion 1: Enable ADC and start conversion 4 - Reserved, must be kept ...
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ST72324B-Auto ADC Data Register Low (ADCDRL) ADCDRL 7 6 Table 73. ADCDRL register description Bit Name 7:2 - Reserved. Forced by hardware to 0. 1:0 D[1:0] LSB of Converted Analog Value Table 74. ADC register map and reset values Address ...
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Instruction set 11 Instruction set 11.1 CPU addressing modes The CPU features 17 different addressing modes which can be classified in 7 main groups (see Table 75). : Table 75. Addressing mode groups Addressing mode Inherent Immediate Direct Indexed Indirect ...
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ST72324B-Auto Table 76. CPU addressing mode overview (continued) Long Indirect Indexed Relative Direct Relative Indirect Bit Direct Bit Indirect Bit Direct Relative Bit Indirect Relative 11.1.1 Inherent All Inherent instructions consist of a single byte. The opcode fully specifies all ...
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Instruction set 11.1.2 Immediate Immediate instructions have two bytes: The first byte contains the opcode and the second byte contains the operand value. . Table 78. Immediate instructions Instruction LD CP BCP AND, OR, XOR ADC, ADD, SUB, SBC 11.1.3 ...
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ST72324B-Auto 11.1.5 Indirect (short, long) The required data byte to do the operation is found by its memory address, located in memory (pointer). The pointer address follows the opcode. The indirect addressing mode consists of two submodes: Indirect (short) The ...
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Instruction set Table 79. Instructions supporting direct, indexed, indirect and indirect indexed addressing modes Short only 11.1.7 Relative mode (direct, indirect) This addressing mode is used to modify the PC register value, by adding an 8-bit signed offset to it. ...
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ST72324B-Auto Table 81. Instruction groups (continued) Group Compare and Tests Logical operations Bit operation Conditional Bit Test and Branch Arithmetic operations ADC Shift and Rotates Unconditional Jump or Call Conditional Branch Interruption management Condition Code Flag modification Instructions CP TNZ ...
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Instruction set Using a prebyte The instructions are described with one to four opcodes. In order to extend the number of available opcodes for an 8-bit CPU (256 opcodes), three different prebyte opcodes are defined. These prebytes modify the meaning ...
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ST72324B-Auto Table 82. Instruction set overview Mnemo Description ADC Add with Carry ADD Addition AND Logical And BCP Bit compare A, memory BRES Bit reset BSET Bit set BTJF Jump if bit is false (0) BTJT Jump if bit is ...
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Instruction set Table 82. Instruction set overview (continued) Mnemo Description JRUGT Jump JRULE Jump Load MUL Multiply NEG Negate (2's compl) NOP No Operation OR OR operation ...
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ST72324B-Auto 12 Electrical characteristics 12.1 Parameter conditions Unless otherwise specified, all voltages are referred to V 12.1.1 Minimum and maximum values Unless otherwise specified the minimum and maximum values are guaranteed in the worst conditions of ambient temperature, supply voltage ...
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Electrical characteristics 12.1.5 Pin input voltage The input voltage measurement on a pin of the device is described in Figure 61. Pin input voltage 12.2 Absolute maximum ratings Stresses above those listed as “absolute maximum ratings” may cause permanent damage ...
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ST72324B-Auto 12.2.2 Current characteristics Table 84. Current characteristics Symbol I Total current into V VDD I Total current out of V VSS Output current sunk by any standard I/O and control pin I Output current sunk by any high sink ...
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Electrical characteristics 12.3 Operating conditions Table 86. Operating conditions Symbol f Internal clock frequency CPU Operating voltage (except Flash Write/Erase Operating Voltage for Flash Write/Erase T Ambient temperature range A Figure 62. f CPU Functionality not guaranteed Note: ...
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ST72324B-Auto 12.4 LVD/AVD characteristics 12.4.1 Operating conditions with LVD Subject to general operating conditions for T Table 87. Operating conditions with LVD Symbol Parameter V Reset release threshold (V IT+(LVD) V Reset generation threshold (V IT-(LVD) V LVD voltage threshold ...
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Electrical characteristics 12.5 Supply current characteristics The following current consumption specified for the ST7 functional operating modes over temperature range does not take into account the clock source current consumption. To obtain the total device consumption, the two current values ...
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ST72324B-Auto 12.5.2 Flash current consumption Table 90. Flash current consumption Symbol Parameter Supply current in Run mode Supply current in Slow (2) mode Supply current in Wait mode I DD Supply current in Slow Wait (2) mode Supply current in ...
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Electrical characteristics 12.5.3 Supply and clock managers The previous current consumption specified for the ST7 functional operating modes over temperature range does not take into account the clock source current consumption. To obtain the total device consumption, the two current ...
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ST72324B-Auto 12.6 Clock and timing characteristics Subject to general operating conditions for V 12.6.1 General timings Table 93. General timings Symbol t Instruction cycle time c(INST) t Interrupt reaction time t v(IT) 1. Data based on typical application software. 2. ...
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Electrical characteristics 12.6.3 Crystal and ceramic resonator oscillators The ST7 internal clock can be supplied with four different crystal/ceramic resonator oscillators. All the information given in this paragraph are based on characterization results with specified typical external components. In the ...
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ST72324B-Auto Figure 65. Typical application with a crystal or ceramic resonator (32 Kbyte Flash and ROM devices) When resonator with integrated capacitors C L2 Table 96. OSCRANGE selection for typical resonators f OSC Supplier (MHz) Murata 16 1. Resonator characteristics ...
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Electrical characteristics Note: To reduce disturbance to the RC oscillator recommended to place decoupling capacitors between V 12.6.5 PLL characteristics Table 98. PLL characteristics Symbol f PLL input frequency range OSC Instantaneous PLL jitter CPU ...
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ST72324B-Auto 12.7.2 Flash memory Table 100. Dual voltage HDFlash memory Symbol f Operating frequency CPU V Programming voltage PP I Supply current current Internal V VPP t Data retention RET N Write/Erase cycles RW ...
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Electrical characteristics 12.8 EMC characteristics Susceptibility tests are performed on a sample basis during product characterization. 12.8.1 Functional electromagnetic susceptibility (EMS) Based on a simple running application on the product (toggling two LEDs through I/O ports), the product is stressed ...
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ST72324B-Auto Table 101. EMS test results Symbol Parameter Voltage limits to be applied on any I/O pin to V FESD induce a functional disturbance Fast transient voltage burst limits applied through 100pF on V FFTB to induce ...
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Electrical characteristics 2. Not tested in production. 12.8.3 Absolute maximum ratings (electrical sensitivity) Based on three different tests (ESD, LU and DLU) using specific measurement methods, the product is stressed in order to determine its performance in terms of electrical ...
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ST72324B-Auto Table 104. Electrical sensitivities Symbol LU Static latch-up class DLU Dynamic latch-up class Parameter Conditions +25°C +85°C +125° 5.5V 4 MHz f OSC +25° Doc ID13466 Rev 4 Electrical ...
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Electrical characteristics 12.9 I/O port pin characteristics 12.9.1 General characteristics Subject to general operating conditions for V Table 105. General characteristics Symbol Parameter Input low level voltage (standard voltage devices) V Input high level voltage IH V Schmitt ...
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ST72324B-Auto Figure 68. Unused I/O pins configured as input 1. I/O can be left unconnected configured as output ( the software. This has the advantage of greater EMC robustness and lower cost. Figure 69. ...
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Electrical characteristics Figure 70. Typical V Figure 71. Typical V Figure 72. Typical V 164/198 (standard ports 1.4 1.2 1 0.8 0.6 Ta =140°C " 0.4 Ta =95°C Ta =25°C 0.2 Ta =-45 °C ...
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ST72324B-Auto Figure 73. Typical V 1 0.9 0.8 0.7 0.6 0.5 0.4 0.3 0.2 0 2.5 Figure 74. Typical 2.5 Figure 75. Typical ...
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Electrical characteristics 12.10 Control pin characteristics 12.10.1 Asynchronous RESET pin Subject to general operating conditions for V Table 107. Asynchronous RESET pin Symbol Parameter V Input low level voltage IL V Input high level voltage IH V Schmitt trigger voltage ...
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ST72324B-Auto Figure 76. RESET pin protection when LVD is enabled Recommended External reset 1. The reset network protects the device against parasitic resets. 2. The output of the external reset circuit must have an open-drain output to drive the ST7 ...
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Electrical characteristics 12.10.2 ICCSEL/V pin PP Subject to general operating conditions for V Table 108. ICCSEL/V Symbol V Input low level voltage IL V Input high level voltage IH I Input leakage current lkg 1. Data based on design simulation ...
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ST72324B-Auto 12.12 Communication interface characteristics 12.12.1 Serial peripheral interface (SPI) The following characteristics are ubject to general operating conditions for V unless otherwise specified. The data is based on design simulation and/or characterization results, not tested in production. When no ...
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Electrical characteristics Figure 79. SPI slave timing diagram with CPHA = 0 SS INPUT CPHA=0 CPOL=0 CPHA=0 CPOL=1 MISO See note 2 OUTPUT MOSI INPUT 1. Measurement points are done at CMOS levels: 0.3xV 2. When no communication is on-going ...
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ST72324B-Auto Figure 81. SPI master timing diagram SS INPUT CPHA = 0 CPOL = 0 CPHA = 0 CPOL = 1 CPHA = 1 CPOL = 0 CPHA = 1 CPOL = 1 t su(MI) MISO INPUT See note 2 ...
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Electrical characteristics Table 111. 10-bit ADC characteristics (continued) Symbol Parameter Conversion time (Sample + Hold) MHz, Speed = 0, CPU MHz t ADC ADC No. of sample capacitor loading cycles No. of Hold conversion ...
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ST72324B-Auto 12.13.1 Analog power supply and reference pins Depending on the MCU pin count, the package may feature separate V analog power supply pins. These pins supply power to the A/D converter cell and function as the high and low ...
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Electrical characteristics 12.13.3 ADC accuracy Table 112. ADC accuracy Symbol Parameter ( Total unadjusted error T ( Offset error O ( Gain error Differential linearity error D ( Integral ...
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ST72324B-Auto 13 Package characteristics In order to meet environmental requirements, ST offers these devices in different grades of ® ECOPACK packages, depending on their level of environmental compliance. ECOPACK specifications, grade definitions and product status are available at: www.st.com. ® ...
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Package characteristics Table 113. 44-pin low profile quad flat package mechanical data Dim 13.2 LQFP32 package characteristics Figure 88. 32-pin low profile quad flat package outline Table 114. 32-pin low profile quad flat package mechanical data Dim. ...
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ST72324B-Auto Table 114. 32-pin low profile quad flat package mechanical data (continued) Dim Min Typ Max 1.00 Number of pins Doc ID13466 Rev 4 Package characteristics inches Min Typ 0.039 32 Max 177/198 ...
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Package characteristics 13.3 Thermal characteristics Table 115. Thermal characteristics Symbol Package thermal resistance (junction to ambient): R LQFP44 10x10 thJA LQFP32 7x7 P Power dissipation D T Maximum junction temperature Jmax 1. The maximum power dissipation is obtained from the ...
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ST72324B-Auto 14 Device configuration and ordering information Each device is available for production in user programmable versions (Flash) as well as in factory coded versions (ROM/FASTROM). ST72324B-Auto devices are ROM versions. ST72P324B-Auto devices are Factory Advanced Service Technique ROM (FASTROM) ...
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Device configuration and ordering information Table 117. Option byte 0 bit description (continued) Bit Name OPT5 - OPT4:3 VD[1:0] OPT2:1 - OPT0 FMP_R Table 118. Option byte 1 bit description Bit Name OPT7 PKG1 OPT6 RSTC OPT5:4 OSCTYPE[1:0] 180/198 Function ...
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ST72324B-Auto Table 118. Option byte 1 bit description (continued) Bit Name OPT3:1 OSCRANGE[2:0] OPT0 PLL OFF Table 119. Package selection (OPT7) Version J K Device configuration and ordering information Function Oscillator range When the resonator oscillator type is selected, these ...
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Device configuration and ordering information 14.1.2 Flash ordering information Figure 90. ST72F324Bxx-Auto Flash commercial product structure Example: Product class ST72 microcontroller Family type F = Flash Sub-family type 324B = 324B sub-family Pin count pins J = ...
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... The followingFigure 91: ST72P324Bxx-Auto FastROM commercial product structure Figure 92: ST72324Bxx-Auto ROM commercial product structure ordering. The STMicroelectronics Sales Organization will be pleased to provide detailed information on contractual points. Caution: The readout protection binary value is inverted between ROM and Flash products. The option byte checksum differs between ROM and Flash ...
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... T = LQFP Temperature range A = -40 ° ° -40 °C to 125 °C Code name Defined by STMicroelectronics. Denotes ROM code, pinout and program memory size. Tape and Reel conditioning options (left blank if Tray Pin 1 left-oriented Pin 1 right-oriented (EIA 481-C compliant) ...
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... B = -40 °C to 105 ° -40 °C to 125 ° -40 °C to 115 °C Code name Defined by STMicroelectronics. Denotes ROM code, pinout and program memory size. Tape and Reel conditioning options (left blank if Tray Pin 1 left-oriented Pin 1 right-oriented (EIA 481-C compliant) ...
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... Reference The FASTROM/ROM code name is assigned by STMicroelectronics. FASTROM/ROM code must be sent in .S19 format. .Hex extension cannot be processed. Device Type/Memory Size/Package (check only one option): ...
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... The Cosmic C Compiler is available in a free version that outputs Kbytes of code. The range of hardware tools includes cost effective ST7-DVP3 series emulators. These tools are supported by the ST7 Toolset from STMicroelectronics, which includes the STVD7 integrated development environment (IDE) with high-level language debugger, editor, project manager and integrated programming interface. ...
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... Device configuration and ordering information Table 120. STMicroelectronics development tools Supported ST7 DVP3 series products Emulator ST72324BJ, ST72F324BJ ST7MDT20- DVP3 ST72324BK, ST72F324BK 1. Add suffix /EU, /UK, /US for the power supply of your region. 14.3.5 Socket and emulator adapter information For information on the type of socket that is supplied with the emulator, refer to the ...
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ST72324B-Auto 15 Known limitations 15.1 All Flash and ROM devices 15.1.1 Safe connection of OSC1/OSC2 pins The OSC1 and/or OSC2 pins must not be left unconnected, otherwise the ST7 main oscillator may start and, in this configuration, could generate an ...
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Known limitations Case 1: Writing to PxOR or PxDDR with global interrupts enabled: LD A,#01 LD sema,A; set the semaphore to '1' LD A,PFDR AND A,#02 LD X,A; store the level before writing to PxOR/PxDDR LD A,#$90 LD PFDDR,A ; ...
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ST72324B-Auto RIM ; reset the interrupt mask LD A,sema ; check the semaphore status CP A,#$01 jrne OUT call call_routine ; call the interrupt routine RIM OUT:RIM JP while_loop .call_routine ; entry to call_routine PUSH A PUSH X PUSH CC ...
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Known limitations Nested interrupt context The symptom does not occur when the interrupts are handled normally, that is, when: ● The interrupt flag is cleared within its own interrupt routine ● The interrupt flag is cleared within any interrupt routine ...
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ST72324B-Auto In the same way, as long as the SBK bit is set, break characters are sent to the TDO pin. This may lead to generate one break more than expected. Occurrence The occurrence of the problem is random and ...
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Known limitations Table 122. Port A and F configuration PLL PA3 Off consequence, for cycle-accurate operations, these configurations are prohibited in either input or output mode. Workaround To avoid this from occurring recommended ...
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ST72324B-Auto 16 Revision history Table 123. Document revision history Date Revision 23-May-2007 23-Jul-2007 1 Initial release Replaced ST72324B-Auto with ST72324Bxx-Auto in document title on cover page. 1 analog peripheral (low current coupling) on page input ports’ with ‘12 input ports’ ...
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Revision history Table 123. Document revision history (continued) Date Revision 23-Jul-2007 (cont’d) 10-Jun-2010 196/198 Table 121: Flash user programmable device types on page - added footnote to order code column - modified order codes - replaced R with TR for ...
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ST72324B-Auto Table 123. Document revision history (continued) Date Revision 12-Jul-2010 Added Section 13.5 on page 178 Updated Figure 90: ST72F324Bxx-Auto Flash commercial product 4 structure on page 182, Figure 91: ST72P324Bxx-Auto FastROM commercial product structure on page 184 Auto ROM ...
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... Information in this document is provided solely in connection with ST products. STMicroelectronics NV and its subsidiaries (“ST”) reserve the right to make changes, corrections, modifications or improvements, to this document, and the products and services described herein at any time, without notice. All ST products are sold pursuant to ST’s terms and conditions of sale. ...