ST72324BJ4-auto STMicroelectronics, ST72324BJ4-auto Datasheet - Page 34

• Manufacturer Part Number: ST72324BJ4-auto
• Description: 8-bit MCU for automotive, 3.8 to 5.5V operating range with 16 Kbyte Flash, 10-bit ADC, 4 timers, SPI, SCI
• Manufacturer: STMicroelectronics

Specifications of ST72324BJ4-auto

• Hdflash Endurance: 100 cycles, data retention 20 years
• Clock Sources: crystal/ceramic resonator oscillators, internal RC oscillator and external clock input
• 4 Power Saving Modes: Slow, Wait, Active Halt, and Halt

Supply, reset and clock management
6.4
Caution:
6.4.1
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Reset sequence manager (RSM)
The reset sequence manager includes three reset sources as shown in
●
●
●
These sources act on the RESET pin and it is always kept low during the delay phase.
The reset service routine vector is fixed at addresses FFFEh-FFFFh in the ST7 memory
map.
The basic reset sequence consists of three phases as shown in
●
●
●
When the ST7 is unprogrammed or fully erased, the Flash is blank and the RESET vector is
not programmed. For this reason, it is recommended to keep the RESET pin in low state
until programming mode is entered, in order to avoid unwanted behavior.
The 256 or 4096 CPU clock cycle delay allows the oscillator to stabilize and ensures that
recovery has taken place from the reset state. The shorter or longer clock cycle delay
should be selected by option byte to correspond to the stabilization time of the external
oscillator used in the application.
The reset vector fetch phase duration is two clock cycles.
Figure 11. Reset sequence phases
Asynchronous external RESET pin
The RESET pin is both an input and an open-drain output with integrated R
resistor. This pull-up has no fixed value but varies in accordance with the input voltage. It
can be pulled low by external circuitry to reset the device. See the
section for more details.
A reset signal originating from an external source must have a duration of at least t
in order to be recognized (see
MCU can enter reset state even in Halt mode.
External reset source pulse
Internal LVD reset
Internal Watchdog reset
Active Phase depending on the reset source
256 or 4096 CPU clock cycle delay (selected by option byte)
Reset vector fetch
ACTIVE PHASE
Doc ID13466 Rev 4
Figure
256 or 4096 CLOCK CYCLES
13). This detection is asynchronous and therefore the
INTERNAL RESET
RESET
Figure
Electrical characteristics
VECTOR
11:
Figure
FETCH
ST72324B-Auto
ON
weak pull-up
12:
h(RSTL)in