ST72324BJ4-auto STMicroelectronics, ST72324BJ4-auto Datasheet - Page 123
ST72324BJ4-auto
Manufacturer Part Number
ST72324BJ4-auto
Description
8-bit MCU for automotive, 3.8 to 5.5V operating range with 16 Kbyte Flash, 10-bit ADC, 4 timers, SPI, SCI
Manufacturer
STMicroelectronics
Datasheet
1.ST72324BJ2-AUTO.pdf
(198 pages)
Specifications of ST72324BJ4-auto
Hdflash Endurance
100 cycles, data retention 20 years
Clock Sources
crystal/ceramic resonator oscillators, internal RC oscillator and external clock input
4 Power Saving Modes
Slow, Wait, Active Halt, and Halt
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ST72324B-Auto
Table 62.
Bit Name
7
6
5
4
3
2
TDRE
RDRF
IDLE
OR
TC
NF
SCISR register description
Transmit Data Register Empty
Transmission Complete
Received Data Ready Flag
Idle line detect
Overrun error
Noise Flag
This bit is set by hardware when the content of the TDR register has been transferred
into the shift register. An interrupt is generated if the TIE bit = 1 in the SCICR2
register. It is cleared by a software sequence (an access to the SCISR register
followed by a write to the SCIDR register).
0: Data is not transferred to the shift register.
1: Data is transferred to the shift register.
Note: Data will not be transferred to the shift register unless the TDRE bit is cleared.
This bit is set by hardware when transmission of a frame containing data is complete.
An interrupt is generated if TCIE = 1 in the SCICR2 register. It is cleared by a
software sequence (an access to the SCISR register followed by a write to the
SCIDR register).
0: Transmission is not complete
1: Transmission is complete
Note: TC is not set after the transmission of a Preamble or a Break.
This bit is set by hardware when the content of the RDR register has been
transferred to the SCIDR register. An interrupt is generated if RIE = 1 in the SCICR2
register. It is cleared by a software sequence (an access to the SCISR register
followed by a read to the SCIDR register).
0: Data is not received
1: Received data is ready to be read
This bit is set by hardware when a Idle Line is detected. An interrupt is generated if
the ILIE = 1 in the SCICR2 register. It is cleared by a software sequence (an access
to the SCISR register followed by a read to the SCIDR register).
0: No idle line is detected
1: Idle line is detected
Note: The IDLE bit is not reset until the RDRF bit has itself been set (that is, a new
idle line occurs).
This bit is set by hardware when the word currently being received in the shift register
is ready to be transferred into the RDR register while RDRF = 1. An interrupt is
generated if RIE = 1 in the SCICR2 register. It is cleared by a software sequence (an
access to the SCISR register followed by a read to the SCIDR register).
0: No overrun error
1: Overrun error is detected
Note: When this bit is set RDR register content is not lost but the shift register is
overwritten.
This bit is set by hardware when noise is detected on a received frame. It is cleared
by a software sequence (an access to the SCISR register followed by a read to the
SCIDR register).
0: No noise is detected
1: Noise is detected
Note: This bit does not generate interrupt as it appears at the same time as the
RDRF bit which itself generates an interrupt.
Doc ID13466 Rev 4
Function
On-chip peripherals
123/198
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