ST10F273Z4 STMicroelectronics, ST10F273Z4 Datasheet - Page 85

• Manufacturer Part Number: ST10F273Z4
• Description: 16-BIT MICROCONTROLLER WITH MAC UNIT, UP TO 832 KBYTES FLASH MEMORY AND UP TO 68 KBYTES RAM
• Manufacturer: STMicroelectronics

Specifications of ST10F273Z4

• Single Voltage Supply: 5 V ±10%

ST10F273Z4
20.3
Figure 18. Asynchronous hardware RESET (EA = 0)
1) Longer than Port0 settling time + PLL synchronization (if needed, that is P0(15:13) changed). Longer than
2) 3 to 8 TCL depending on clock source selection.
Exit from asynchronous reset state
When the RSTIN pin is pulled high, the device restarts: as already mentioned, if internal
FLASH is used, the restarting occurs after the embedded FLASH initialization routine is
completed. The system configuration is latched from Port0: ALE, RD and WR/WRL pins are
driven to their inactive level. The ST10F273Z4 starts program execution from memory
location 00'0000h in code segment 0. This starting location will typically point to the general
initialization routine. Timing of asynchronous Hardware Reset sequence are summarized in
Figure 17
Synchronous reset (warm reset)
A synchronous reset is triggered when RSTIN pin is pulled low while RPD pin is at high
level. In order to properly activate the internal reset logic of the device, the RSTIN pin must
be held low, at least, during 4 TCL (2 periods of CPU clock): refer also to
details on minimum reset pulse duration. The I/O pins are set to high impedance and
RSTOUT pin is driven low. After RSTIN level is detected, a short duration of a maximum of
12 TCL (six periods of CPU clock) elapses, during which pending internal hold states are
cancelled and the current internal access cycle if any is completed. External bus cycle is
aborted. The internal pull-down of RSTIN pin is activated if bit BDRSTEN of SYSCON
500ns to take into account of Input Filter on RSTIN pin
RPD
RSTIN
RSTF
(After Filter)
P0[15:13]
P0[12:2]
P0[1:0]
ALE
RST
and
Figure
not transparent
not transparent
18.
≤ 500 ns
≥ 50 ns
1)
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transparent
transparent
system start-up configuration
Latching point of Port0 for
≤ 500 ns
≥ 50 ns
3..4 TCL
3..8 TCL
Section 20.1
2)
not t.
not t.
not t.
System reset
8 TCL
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for