ST10F273Z4 STMicroelectronics, ST10F273Z4 Datasheet - Page 79

• Manufacturer Part Number: ST10F273Z4
• Description: 16-BIT MICROCONTROLLER WITH MAC UNIT, UP TO 832 KBYTES FLASH MEMORY AND UP TO 68 KBYTES RAM
• Manufacturer: STMicroelectronics

Specifications of ST10F273Z4

• Single Voltage Supply: 5 V ±10%

ST10F273Z4
20
20.1
System reset
System reset initializes the MCU in a predefined state. There are six ways to activate a reset
state. The system start-up configuration is different for each case as shown in
Table 50.
1. RSTIN pulse should be longer than 500ns (Filter) and than settling time for configuration of Port0.
2. See next
3. The RPD status has no influence unless Bidirectional Reset is activated (bit BDRSTEN in SYSCON): RPD
Input filter
On RSTIN input pin an on-chip RC filter is implemented. It is sized to filter all the spikes
shorter than 50ns. On the other side, a valid pulse shall be longer than 500ns to grant that
ST10 recognizes a reset command. In between 50ns and 500ns a pulse can either be
filtered or recognized as valid, depending on the operating conditions and process
variations.
For this reason all minimum durations mentioned in this Chapter for the different kind of
reset events shall be carefully evaluated taking into account of the above requirements.
In particular, for Short Hardware Reset, where only 4 TCL is specified as minimum input
reset pulse duration, the operating frequency is a key factor. Examples:
●
●
Power-on reset
Asynchronous hardware reset
Synchronous long hardware
reset
Synchronous short hardware
reset
Watchdog timer reset
Software reset
low inhibits the Bidirectional reset on SW and WDT reset events, that is RSTIN is not activated (refer to
Sections 20.4,
For a CPU clock of 64 MHz, 4 TCL is 31.25ns, so it would be filtered. In this case the
minimum becomes the one imposed by the filter (that is 500ns).
For a CPU clock of 4 MHz, 4 TCL is 500ns. In this case the minimum from the formula
is coherent with the limit imposed by the filter.
Reset Source
Section 20.1
Reset event definition
20.5
and 20.6).
for more details on minimum reset pulse duration
SHWR
WDTR
PONR
LHWR
SWR
Flag
Status
RPD
High
High
Low
Low
(2)
(3)
Power-on
t
t
t
t
WDT overflow
SRST instruction execution
RSTIN
RSTIN
RSTIN
RSTIN
>
> max(4 TCL, 500ns)
> (1032 + 12)TCL + max(4 TCL, 500ns)
≤ (1032 + 12)TCL + max(4 TCL, 500ns)
(1)
Conditions
System reset
Table
50.
79/188