ST10F273Z4 STMicroelectronics, ST10F273Z4 Datasheet - Page 157

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ST10F273Z4

Manufacturer Part Number
ST10F273Z4
Description
16-BIT MICROCONTROLLER WITH MAC UNIT, UP TO 832 KBYTES FLASH MEMORY AND UP TO 68 KBYTES RAM
Manufacturer
STMicroelectronics
Datasheet

Specifications of ST10F273Z4

Single Voltage Supply
5 V ±10%

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ST10F273Z4
24.8.16
Table 78.
t
t
t
t
t
t
t
t
t
t
t
t
t
t
t
t
t
t
t
t
t
5
6
7
8
9
10
11
12
13
14
15
16
17
18
19
22
23
25
27
38
39
Symbol
CC ALE high time
CC Address setup to ALE
CC Address hold after ALE
CC
CC
CC
CC
CC
CC
SR
SR
SR ALE low to valid data in
SR
SR
SR Data float after
CC Data valid to WR
CC Data hold after WR
CC ALE rising edge after RD, WR
CC
CC ALE falling edge to latched CS
SR
ALE falling edge to RD, WR
(with RW-delay)
ALE falling edge to RD, WR
(no RW-delay)
Address float after RD, WR
(with
Address float after RD, WR
(no
RD, WR low time
(with RW-delay)
RD, WR low time
(no RW-delay)
RD to valid data in
(with RW-delay)
RD to valid data in
(no RW-delay)
Address/Unlatched CS to valid
data in
Data hold after RD
rising edge
Address/unlatched CS hold
after RD, WR
Latched CS low to valid data
in
Multiplexed bus
V
ALE cycle time = 6 TCL + 2t
Multiplexed bus timings
DD
RW-delay)1
RW-delay)1
= 5V ± 10%, V
Parameter
RD1
SS
= 0V, T
– 8.5 + t
15.5 + t
A
1.5 + t
– 4 – t
28 + t
10 + t
15 + t
10 + t
A
4 + t
4 + t
4 + t
4 + t
Min.
+ t
= –40 °C to +125 °C, CL = 50 pF,
0
C
f
TCL = 12.5 ns
A
A
A
F
CPU
C
C
F
F
A
A
+ t
C
A
F
= 40 MHz
16.5 + t
(75ns at 40 MHz CPU clock without wait states)
17.5 + t
20 + 2t
18.5 + t
16.5 + t
10 – t
6 + t
Max.
18.5
6
C
A
A
C
A
+ 2t
+ t
+ t
C
F
C
C
A
2TCL – 9.5 + t
3TCL – 9.5 + t
2TCL – 8.5 + t
2TCL – 15 + t
2TCL – 10 + t
2TCL – 15 + t
TCL – 8.5 + t
TCL – 8.5 + t
TCL – 8.5 + t
TCL – 11 + t
– 8.5 + t
– 4 – t
Min.
1/2 TCL = 1 to 64 MHz
0
Variable CPU clock
A
A
Electrical characteristics
A
A
A
A
C
F
F
C
C
F
3TCL – 20 + t
4TCL – 30+ 2t
3TCL – 21+ t
2TCL – 8.5 + t
2TCL – 19 + t
3TCL – 19 + t
TCL + 6
10 – t
Max.
6
A
C
A
A
+ 2t
+ t
+ t
C
C
F
157/188
C
A
C
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns

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