ST10F273Z4 STMicroelectronics, ST10F273Z4 Datasheet - Page 163

• Manufacturer Part Number: ST10F273Z4
• Description: 16-BIT MICROCONTROLLER WITH MAC UNIT, UP TO 832 KBYTES FLASH MEMORY AND UP TO 68 KBYTES RAM
• Manufacturer: STMicroelectronics

Specifications of ST10F273Z4

• Single Voltage Supply: 5 V ±10%

ST10F273Z4
24.8.17
Table 79.
t
t
t
t
t
t
t
t
t
t
t
t
t
t
t
t
t
t
t
5
6
80
81
12
13
14
15
16
17
18
20
21
22
24
26
28
28h
38
Symbol
CC
CC
CC
CC
CC
CC
SR
SR
SR
SR
SR
SR
SR
CC
CC
CC
CC
CC
CC
ALE high time
Address setup to ALE
Address/Unlatched CS
setup to RD, WR
(with RW-delay)
Address/Unlatched CS
setup to RD, WR
(no RW-delay)
RD, WR low time
RD, WR low time
RD to valid data in
RD to valid data in
ALE low to valid data in
Address/Unlatched CS to
valid data in
Data hold after RD
rising edge
Data float after RD rising
edge (with RW-delay)
Data float after RD rising
edge (no RW-delay)
Data valid to WR
Data hold after WR
ALE rising edge after RD,
WR
Address/Unlatched CS
hold after RD, WR
Address/Unlatched CS
hold after WRH
ALE falling edge to
Latched CS
(with RW-delay)
(no RW-delay)
(with RW-delay)
(no RW-delay)
Demultiplexed bus
V
ALE cycle time = 4 TCL + 2t
Demultiplexed bus timings
DD
= 5V ± 10%, V
Parameter
(2)
(1)
3(1)
SS
= 0V, T
12.5 + 2t
0.5 + 2t
15.5 + t
–10 + t
1.5 + t
– 5 + t
– 4 – t
28 + t
10 + t
4 + t
4 + t
0 + t
Min.
–
–
–
–
0
–
–
A
F
A
TCL = 12.5 ns
A
F
F
+ t
C
C
CPU
A
A
F
F
= –40 °C to +125 °C, CL = 50 pF,
A
C
A
C
= 40 MHz
+ t
17.5 + t
20 + 2t
F
18.5 + t
16.5 + t
(50ns at 40 MHz CPU clock without wait states)
6 + t
4 + t
6 – t
Max.
–
–
–
–
–
–
–
–
–
–
–
–
A
A
C
A
F
+ t
+ t
C
F
C
C
2TCL – 9.5 + t
3TCL – 9.5 + t
TCL – 12 + 2t
2TCL – 15 + t
TCL – 8.5 + t
TCL – 8.5 + t
TCL – 11 + t
2TCL – 12.5
–10 + t
– 5 + t
– 4 – t
0 + t
+ 2t
Min.
–
–
–
–
0
–
–
1/2 TCL = 1 to 64 MHz
Variable CPU Clock
A
F
F
A
F
A
A
F
A
C
C
C
Electrical characteristics
2TCL – 8.5 + t
4TCL – 30 + 2t
TCL – 8.5 + t
3TCL – 20 + t
2TCL – 19 + t
3TCL – 19 + t
6 – t
Max.
–
–
–
–
–
–
–
–
–
–
–
–
A
F
F
A
A
+ 2t
+ 2t
+ t
C
C
+ t
C
A
163/188
C
A
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns