ST10F273Z4 STMicroelectronics, ST10F273Z4 Datasheet - Page 141

• Manufacturer Part Number: ST10F273Z4
• Description: 16-BIT MICROCONTROLLER WITH MAC UNIT, UP TO 832 KBYTES FLASH MEMORY AND UP TO 68 KBYTES RAM
• Manufacturer: STMicroelectronics

Specifications of ST10F273Z4

• Single Voltage Supply: 5 V ±10%

ST10F273Z4
(sampled voltage on C
must be designed to respect the following relation:
The formula above provides a constraints for external network design, in particular on
resistive path.
A second aspect involving the capacitance network shall be considered. Assuming the three
capacitances C
equivalent circuit reported in Figure 38), when the sampling phase is started (A/D switch
close), a charge sharing phenomena is installed.
Figure 39. Charge sharing timing diagram during sampling phase
In particular two different transient periods can be distinguished (see Figure 39):
●
●
A first and quick charge transfer from the internal capacitance C
sampling capacitance C
considering a worst case (since the time constant in reality would be faster) in which
C
are in series, and the time constant is:
This relation can again be simplified considering only C
condition. In reality, the transient is faster, but the A/D Converter circuitry has been
designed to be robust also in the very worst case: the sampling time T
longer than the internal time constant:
The charge of C
voltage V
A second charge transfer involves also C
capacitance) through the resistance R
and C
P2
is reported in parallel to C
S
were in parallel to C
A1
V
V
V
V
F
CS
, C
A
A2
A1
on the capacitance according to the following equation:
P1
1
P1
and C
S
) and the sum of R
and C
Voltage transient on C
V A1
V A
P2
S
⋅
P2
(
⋅
2
initially charged at the source voltage V
occurs (C
C S
R S
----------------------------------------------------------------------------- -
τ 1
P1
is redistributed also on C
τ 1
+
=
P1
+
(since the time constant in reality would be faster), the
C P1
<
(
R F
R SW
(call C
(
R SW
+
S
+
R L
is supposed initially completely discharged):
C P2
S
R EQ
+
L
: again considering the worst case in which C
P
+ R
+
S
R AD
+
T
= C
F
R AD
)
R SW
S
(that is typically bigger than the on-chip
F
=
)
P1
+ R
∆V < 0.5 LSB
⋅
t
V A
)
---------------------- -
C P
C P C S
⋅ << T
+
+ C
C S
L
⋅
R AD
+
(
+ R
⋅
C P1
P2
C S
S
τ
τ
S
), the two capacitance C
SW
1
2
<
, determining a new value of the
< (R
= R
S
+
1
-- - LSB
2
+ R
as an additional worst
C P2
L
SW
(C
Electrical characteristics
AD
)
S
+ R
, the external circuit
+ C
P1
A
AD
and C
P1
(refer to the
) C
S
+ C
S
is always much
<< T
P2
P2
)
to the
S
P
and C
141/188
P2
S