ST10F273Z4 STMicroelectronics, ST10F273Z4 Datasheet - Page 149

• Manufacturer Part Number: ST10F273Z4
• Description: 16-BIT MICROCONTROLLER WITH MAC UNIT, UP TO 832 KBYTES FLASH MEMORY AND UP TO 68 KBYTES RAM
• Manufacturer: STMicroelectronics

Specifications of ST10F273Z4

• Single Voltage Supply: 5 V ±10%

ST10F273Z4
24.8.7
24.8.8
Phase locked loop (PLL)
For all other combinations of pins P0.15-13 (P0H.7-5) during reset the on-chip phase locked
loop is enabled and it provides the CPU clock (see
frequency by the factor F which is selected via the combination of pins P0.15-13 (f
f
the input clock. This synchronization is done smoothly, so the CPU clock frequency does not
change abruptly.
Due to this adaptation to the input clock the frequency of f
locked to f
individual TCLs.
The timings listed in the AC Characteristics that refer to TCLs therefore must be calculated
using the minimum TCL that is possible under the respective circumstances.
The real minimum value for TCL depends on the jitter of the PLL. The PLL tunes f
keep it locked on f
one TCL period.
This is especially important for bus cycles using wait states and e.g. for the operation of
timers, serial interfaces, etc. For all slower operations and longer periods (e.g. pulse train
generation or measurement, lower Baud rates, etc.) the deviation caused by the PLL jitter is
negligible. Refer to next
Voltage controlled oscillator
The ST10F273Z4 implements a PLL which combines different levels of frequency dividers
with a Voltage Controlled Oscillator (VCO) working as frequency multiplier. In the following
table, a detailed summary of the internal settings and VCO frequency is reported.
Table 71.
The PLL input frequency range is limited to 1 to 3.5 MHz, while the VCO oscillation range is
64 to 128 MHz. The CPU clock frequency range when PLL is used is 16 to 64 MHz.
XTAL
(P0H.7-5)
1
1
1
1
0
0
0
0
P0.15-13
1
1
0
0
1
1
0
0
x F). With every F’th transition of f
1 4 to 8 MHz
0 5.3 to 10.6 MHz
1 4 to 8 MHz
0 6.4 to 12 MHz
1 1 to 64 MHz
0 4 to 6.4 MHz
1 4 to 12 MHz
0 4 MHz
XTAL
XTAL frequency
Internal PLL divider mechanism
. The slight variation causes a jitter of f
XTAL
. The relative deviation of TCL is the maximum when it is referred to
1)
Section 24.8.9: PLL jitter
prescaler
F
F
F
XTAL
XTAL
XTAL
Input
–
–
/ 4
/ 2
/ 2
XTAL
Multiply
the PLL circuit synchronizes the CPU clock to
by
64
48
64
40
40
64
PLL bypassed
PLL bypassed
for more details.
PLL
Table
Divide by
CPU
4
2
2
2
70). The PLL multiplies the input
which also effects the duration of
CPU
is constantly adjusted so it is
prescaler
Electrical characteristics
F
Output
PLL
–
–
–
/ 2
CPU frequency
f
CPU
F
F
F
F
F
F
F
F
XTAL
XTAL
XTAL
XTAL
XTAL
XTAL
XTAL
= f
XTAL
CPU
CPU
XTAL
x 10
x 16
149/188
x 4
x 3
x 8
x 5
x 1
/ 2
to
=
x F