ST10F273Z4 STMicroelectronics, ST10F273Z4 Datasheet - Page 164

• Manufacturer Part Number: ST10F273Z4
• Description: 16-BIT MICROCONTROLLER WITH MAC UNIT, UP TO 832 KBYTES FLASH MEMORY AND UP TO 68 KBYTES RAM
• Manufacturer: STMicroelectronics

Specifications of ST10F273Z4

• Single Voltage Supply: 5 V ±10%

Electrical characteristics
Table 79.
1. RW-delay and t
2.
164/188
t
t
t
t
t
t
t
t
t
t
t
t
t
t
39
41
82
83
46
47
48
49
50
51
53
68
55
57
Symbol
address changes before the end of RD have no impact on read cycles.
Read data are latched with the same clock edge that triggers the address change and the rising RD edge. Therefore
SR
CC
CC
CC
SR
SR
CC
CC
CC
SR
SR
SR
CC
CC
Latched CS low to Valid
Data in
Latched CS hold after RD,
WR
Address setup to RdCS,
WrCS (with RW-delay)
Address setup to RdCS,
WrCS (no RW-delay)
RdCS to Valid Data in
(with RW-delay)
RdCS to Valid Data in
(no RW-delay)
RdCS, WrCS Low Time
(with RW-delay)
RdCS, WrCS Low Time
(no RW-delay)
Data valid to WrCS
Data hold after RdCS
Data float after RdCS
(with RW-delay)
Data float after RdCS
(no RW-delay)
Address hold after
RdCS, WrCS
Data hold after WrCS
Demultiplexed bus timings (continued)
A
refer to the next following bus cycle
Parameter
3
3
– 8.5 + t
15.5 + t
14 + 2t
2 + 2t
28 + t
10 + t
2 + t
2 + t
Min.
–
–
–
0
–
–
F
TCL = 12.5 ns
F
F
A
C
C
CPU
A
C
F
= 40 MHz
16.5 + t
16.5 + t
16.5 + t
4 + t
4 + t
Max.
–
–
–
–
–
–
–
–
–
C
C
F
+ 2t
C
F
A
2TCL – 11 + 2t
TCL –10.5 + 2t
2TCL – 9.5 + t
3TCL – 9.5 + t
TCL – 10.5 + t
TCL – 10.5 + t
2TCL – 15 + t
– 8.5 + t
Min.
–
–
–
0
–
–
1/2 TCL = 1 to 64 MHz
Variable CPU Clock
F
C
C
C
F
F
A
A
3TCL – 21 + t
2TCL – 8.5 + t
2TCL – 21 + t
3TCL – 21 + t
TCL – 8.5 + t
Max.
–
–
–
–
–
–
–
–
–
ST10F273Z4
C
+ 2t
F
C
C
F
A
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns