ST10F273Z4 STMicroelectronics, ST10F273Z4 Datasheet - Page 20

• Manufacturer Part Number: ST10F273Z4
• Description: 16-BIT MICROCONTROLLER WITH MAC UNIT, UP TO 832 KBYTES FLASH MEMORY AND UP TO 68 KBYTES RAM
• Manufacturer: STMicroelectronics

Specifications of ST10F273Z4

• Single Voltage Supply: 5 V ±10%

Pin data
Table 2.
20/188
RSTOUT
Symbol
RSTIN
XTAL1
XTAL2
XTAL3
XTAL4
V
V
RPD
NMI
AGND
V
V
V
AREF
DD
SS
18
Pin description (continued)
72,82,93,
109, 126,
110, 127,
17, 46,
18,45,
55,71,
83,94,
138
137
143
144
140
141
142
136
139
Pin
37
38
84
56
Type
O
O
O
I
I
I
I
-
-
-
-
-
-
XTAL1 Main oscillator amplifier circuit and/or external clock input.
XTAL2 Main oscillator amplifier circuit output.
To clock the device from an external source, drive XTAL1 while leaving XTAL2
unconnected. Minimum and maximum high / low and rise / fall times specified in
the AC Characteristics must be observed.
XTAL3 32 kHz oscillator amplifier circuit input
XTAL4 32 kHz oscillator amplifier circuit output
When 32 kHz oscillator amplifier is not used, to avoid spurious consumption,
XTAL3 shall be tied to ground while XTAL4 shall be left open. Besides, bit OFF32
in RTCCON register shall be set. 32 kHz oscillator can only be driven by an
external crystal, and not by a different clock source.
Reset Input with CMOS Schmitt-Trigger characteristics. A low level at this pin for
a specified duration while the oscillator is running resets the ST10F273Z4. An
internal pull-up resistor permits power-on reset using only a capacitor connected
to V
SYSCON register), the RSTIN line is pulled low for the duration of the internal
reset sequence.
Internal Reset Indication Output. This pin is driven to a low level during
hardware, software or watchdog timer reset.
(end of initialization) instruction is executed.
Non-Maskable Interrupt Input. A high to low transition at this pin causes the CPU
to vector to the NMI trap routine. If bit PWDCFG = ‘0’ in SYSCON register, when
the PWRDN (power down) instruction is executed, the NMI pin must be low in
order to force the ST10F273Z4 to go into power down mode. If NMI is high and
PWDCFG =’0’, when PWRDN is executed, the part will continue to run in normal
mode.
If not used, pin NMI should be pulled high externally.
A/D converter reference voltage and analog supply
A/D converter reference and analog ground
Timing pin for the return from interruptible power down mode and synchronous /
asynchronous reset selection.
Digital supply voltage = + 5V during normal operation, idle and power down
modes.
It can be turned off when Stand-by RAM mode is selected.
Digital ground
1.8V decoupling pin: a decoupling capacitor (typical value of 10nF, max 100nF)
must be connected between this pin and nearest V
SS
. In bidirectional reset mode (enabled by setting bit BDRSTEN in
Function
RSTOUT
SS
remains low until the EINIT
pin.
ST10F273Z4