LPC3130_3131 NXP Semiconductors, LPC3130_3131 Datasheet - Page 7

• Manufacturer Part Number: LPC3130_3131
• Description: The NXP LPC3130/3131 combine an 180 MHz ARM926EJ-S CPU core, high-speed USB2
• Manufacturer: NXP Semiconductors

NXP Semiconductors
Table 4.
Pin names with prefix m are multiplexed pins. See
LPC3130_3131_1
Preliminary data sheet
Pin name
USB_VDDA12_PLL
USB_VDDA33_DRV
USB_VDDA33
USB_VSSA_TERM
USB_GNDA
USB_VSSA_REF
JTAG
JTAGSEL
TDI
TRST_N
TCK
TMS
SCAN_TDO
ARM_TDO
BUF_TRST_N
BUF_TCK
BUF_TMS
UART
mUART_CTS_N
mUART_RTS_N
UART_RXD
UART_TXD
I
I2C_SDA0
I2C_SCL0
I2C_SDA1
I2C_SCL1
Serial Peripheral Interface
SPI_CS_OUT0
SPI_SCK
SPI_MISO
2
C master/slave interface
[3]
[3]
[3]
[3]
Pin description
[3]
[3]
[3]
[3][4]
[3][4]
BGA
Ball
L1
M2
P1
L3
N1
K4
N11
K9
P13
M14
P10
F10
E11
F11
D13
D14
N13
P14
P12
N12
C10
D10
E12
E13
A7
A8
C8
Digital
I/O
level
[1]
SUP1
SUP3
SUP3
SUP3
SUP3
SUP3
SUP3
SUP3
SUP3
SUP3
SUP3
SUP3
SUP3
SUP3
SUP3
SUP3
SUP3
SUP3
SUP3
SUP3
SUP3
SUP3
SUP3
SUP3
Application
function
Supply
Supply
Supply
Ground
Ground
Ground
DI
DI
DI
DI
DI
DO
DO
DO
DO
DO
DI / GPIO
DO / GPIO
DI / GPIO
DO / GPIO
DIO
DIO
DIO
DIO
DO
DIO
DIO
Rev. 1 — 9 February 2009
Table 10
Pin
state
after
reset
-
-
-
-
-
-
I
I
I
I
I
O/Z
O
O
O
O
I
O
I
O
I
I
O
O
O
I
I
for pin function selection of multiplexed pins.
Low-cost, low-power ARM926EJ-S microcontrollers
Cell
Type
PS3
PS3
PS3
CG1
CG1
CG1
DIO1
DIO1
DIO1
DIO1
DIO1
DIO1
DIO1
DIO1
DIO1
DIO1
DIO1
DIO1
DIO1
DIO1
IICD
IICC
DIO1
DIO1
DIO4
DIO4
DIO4
[2]
Description
USB PLL supply
USB Analog supply for driver
USB Analog supply for PHY
USB Analog ground for clean reference for on
chip termination resistors
USB Analog ground
USB Analog ground for clean reference
JTAG selection. Controls output function of
SCAN_TDO and ARM_TDO signals.
JTAG Data Input
JTAG Reset Input
JTAG Clock Input
JTAG Mode Select Input
JTAG TDO signal from scan TAP controller. Pin
state is controlled by JTAGSEL.
JTAG TDO signal from ARM926 TAP
controller.
Buffered TRST_N out signal. Used for
connecting an on board TAP controller (FPGA,
DSP, etc.).
Buffered TCK out signal. Used for connecting
an on board TAP controller (FPGA, DSP, etc.).
Buffered TMS out signal. Used for connecting
an on board TAP controller (FPGA, DSP, etc.).
UART Clear To Send (active LOW)
UART Ready To Send (active LOW)
UART Serial Input
UART Serial Output
I
I
I
I
SPI Chip Select Output (Master)
SPI Clock Input (Slave) / Clock Output
(Master)
SPI Data Input (Master) / Data Output (Slave)
2
2
2
2
C Data Line
C Clock line
C Data Line
C Clock line
LPC3130/3131
© NXP B.V. 2009. All rights reserved.
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