LPC3130_3131 NXP Semiconductors, LPC3130_3131 Datasheet - Page 18

• Manufacturer Part Number: LPC3130_3131
• Description: The NXP LPC3130/3131 combine an 180 MHz ARM926EJ-S CPU core, high-speed USB2
• Manufacturer: NXP Semiconductors

NXP Semiconductors
LPC3130_3131_1
Preliminary data sheet
6.8 Internal RAM memory
6.9 Memory Card Interface (MCI)
Table 8.
The ISRAM (Internal Static RAM Memory) controller module is used as controller
between the AHB bus and the internal RAM memory. The internal RAM memory can be
used as working memory for the ARM processor and as temporary storage to execute the
code that is loaded by boot ROM from external devices such as SPI-flash, NAND flash,
and SD/MMC cards.
This module has the following features:
The MCI controller interface can be used to access memory cards according to the
Secure Digital (SD) and Multi-Media Card (MMC) standards. The host controller can be
used to interface to small form factor expansion cards compliant to the SDIO card
standard as well. Finally, the MCI supports CE-ATA 1.1 compliant hard disk drives.
This module has the following features:
Boot mode
NAND
SPI
DFU
SD/MMC
Reserved 0
NOR flash
UART
Test
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Capacity of 96 kB (LPC3130) or 192 kB (LPC3131)
On LPC3131 implemented as two independent 96 kB memory banks
One 8-bit wide interface.
Supports high-speed SD, versions 1.01, 1.10 and 2.0.
Supports SDIO version 1.10.
Supports MMCplus, MMCmobile and MMCmicro cards based on MMC 4.1.
Supports SDHC memory cards.
CRC generation and checking.
LPC3130/3131 boot modes
GPIO0 GPIO1 GPIO2 Description
0
0
0
0
1
1
1
1
0
0
1
1
0
0
1
1
Rev. 1 — 9 February 2009
0
1
0
1
0
1
0
1
Low-cost, low-power ARM926EJ-S microcontrollers
Boots from NAND flash. If proper image is not found,
boot ROM will switch to DFU boot mode.
Boot from SPI NOR flash connected to SPI_CS_OUT0. If
proper image is not found, boot ROM will switch to DFU
boot mode.
Device boots via USB using DFU class specification.
Boot ROM searches all the partitions on the
SD/MMC/SDHC/MMC+/eMMC/eSD card for boot image.
If partition table is missing, it will start searching from
sector 0. A valid image is said to be found if a valid image
header is found, followed by a valid image. If a proper
image is not found, boot ROM will switch to DFU boot
mode.
Reserved for testing.
Boot from parallel NOR flash connected to
EBI_NSTCS_1.
Boot ROM tries to download boot image from UART
((115200 – 8 – n -1) assuming 12 MHz FFAST clock).
Boot ROM is testing ISRAM using memory pattern test.
After test switches to UART boot mode.
LPC3130/3131
© NXP B.V. 2009. All rights reserved.
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