LPC3130_3131 NXP Semiconductors, LPC3130_3131 Datasheet - Page 44

• Manufacturer Part Number: LPC3130_3131
• Description: The NXP LPC3130/3131 combine an 180 MHz ARM926EJ-S CPU core, high-speed USB2
• Manufacturer: NXP Semiconductors

NXP Semiconductors
LPC3130_3131_1
Preliminary data sheet
Fig 13. LCD timing (Motorola 6800 mode)
mLCD_DB[15:0] (16 bit mode),
mLCD_DB[15:0] (16 bit mode),
mLCD_DB[15:12] (4 bit mode)
mLCD_DB[15:12] (4 bit mode)
mLCD_DB[15:8] (8 bit mode),
mLCD_DB[15:8] (8 bit mode),
9.1.2 Motorola 6800 mode
mLCD_RW_WR
mLCD_E_RD
Table 15.
C
[1]
Symbol
t
t
t
t
t
t
t
t
t
t
mLCD_CSB
su(A)
h(A)
cy(a)
r
f
su(D)
h(D)
d(QV)
dis(Q)
w(en)
L
mLCD_RS,
= 25 pF, T
Timing is derived from the LCD Interface Control Register fields: INVERT_CS = 1; MI = 1; PS = 0;
INVERT_E_RD = 0. See LPC3130/3131 user manual .
Dynamic characteristics: LCD controller in Motorola 6800 mode
Parameter
address set-up time
address hold time
access cycle time
rise time
fall time
data input set-up time
data input hold time
data output valid delay time
data output disable time
enable pulse width
amb
= 40 C to +85 C, unless otherwise specified; V
Rev. 1 — 9 February 2009
t
su(A)
t
r
Low-cost, low-power ARM926EJ-S microcontrollers
t
d(QV)
Conditions
write cycle
read cycle
t
w(en)
t
su(D)
t
f
t
cy(a)
t
t
h(D)
h(A)
t
dis(Q)
[1]
Min
-
-
-
2
2
<tbd>
<tbd>
-
-
-
-
LPC3130/3131
DD(IO)
Typ
1
2
5
-
-
-
-
2
2
2
1
= 1.8 V and 2.8 V (SUP8).
LCDCLK
LCDCLK
LCDCLK
LCDCLK
LCDCLK
LCDCLK
LCDCLK
© NXP B.V. 2009. All rights reserved.
read access
write access
002aae208
Max
-
-
-
5
5
-
-
-
-
-
-
44 of 68
Unit
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns