LPC3130_3131 NXP Semiconductors, LPC3130_3131 Datasheet - Page 34

• Manufacturer Part Number: LPC3130_3131
• Description: The NXP LPC3130/3131 combine an 180 MHz ARM926EJ-S CPU core, high-speed USB2
• Manufacturer: NXP Semiconductors

NXP Semiconductors
LPC3130_3131_1
Preliminary data sheet
6.26.3 Supply domains
6.27 Timer module
6.28 Pulse Width Modulation (PWM) module
The EBI unit between the NAND flash interface and the MPMC contains an arbiter that
determines which interface is muxed to the outside world. Both NAND flash and
SDRAM/SRAM initiate a request to the EBI unit. This request is granted using round-robin
arbitration (see
As is shown in
different supply domain than the LCD interface. The EBI control and address signals are
muxed with the LCD interface signals and are part of supply domain SUP8. The
SDRAM/SRAM data lines are shared with the NAND flash through the EBI and are part of
supply domain SUP4. Therefore the following rules apply for connecting memories:
The LPC3130/3131 contains four fully independent timer modules, which can be used to
generate interrupts after a pre-set time interval has elapsed.
This module has the following features:
This PWM can be used to generate a pulse width modulated or a pulse density modulated
signal. With an external low pass filter, the module can be used to generate a
low-frequency analog signal. A typical use of the output of the module is to control the
backlight of an LCD display.
This module has the following features:
1. SDRAM and bus-based LCD or SRAM: This is the MPMC mode. The supply voltage
2. Dedicated LCD interface only: This is the LCD mode. The NAND flash supply voltage
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for SDRAM/SRAM/bus-based LCD and NAND flash must be the same.The dedicated
LCD interface is not available in this MPMC mode.
(SUP4) can be different from the LCD supply voltage (SUP8).
Each timer is a 32 bit wide down-counter with selectable pre-scale. The pre-scaler
allows using either the module clock directly or the clock divided by 16 or 256.
Two modes of operation:
– Free-running timer: The timer generates an interrupt when the counter reaches
– Periodic timer: The timer generates an interrupt when the counter reaches zero. It
At any time the current timer value can be read.
At any time the value in the load register may be re-written, causing the timer to
restart.
Supports Pulse Width Modulation (PWM) with software controlled duty cycle.
Supports Pulse Density Modulation (PDM) with software controlled pulse density.
zero. The timer wraps around to 0xFFFFFFFF and continues counting down.
reloads the value from a load register and continues counting down from that
value. An interrupt will be generated every time the counter reaches zero. This
effectively gives a repeated interrupt at a regular interval.
Figure 9
Section
Rev. 1 — 9 February 2009
6.6).
the EBI (NAND flash/MPMC-control/data) is connected to a
Low-cost, low-power ARM926EJ-S microcontrollers
LPC3130/3131
© NXP B.V. 2009. All rights reserved.
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