ATmega48PA Automotive Atmel Corporation, ATmega48PA Automotive Datasheet - Page 209

• Manufacturer Part Number: ATmega48PA Automotive
• Manufacturer: Atmel Corporation

21.8
21.8.1
21.8.2
21.8.3
9223B–AVR–09/11
Register Description
UDRn – USART MSPIM I/O Data Register
UCSRnA – USART MSPIM Control and Status Register n A
UCSRnB – USART MSPIM Control and Status Register n B
The following section describes the registers used for SPI operation using the USART.
The function and bit description of the USART data register (UDRn) in MSPI mode is identical
to normal USART operation. See “UDRn – USART I/O Data Register n” on page 196.
• Bit 7 – RXCn: USART Receive Complete
This flag bit is set when there are unread data in the receive buffer and cleared when the
receive buffer is empty (i.e., does not contain any unread data). If the Receiver is disabled, the
receive buffer will be flushed and consequently the RXCn bit will become zero. The RXCn
Flag can be used to generate a Receive Complete interrupt (see description of the RXCIEn
bit).
• Bit 6 – TXCn: USART Transmit Complete
This flag bit is set when the entire frame in the Transmit Shift Register has been shifted out
and there are no new data currently present in the transmit buffer (UDRn). The TXCn Flag bit
is automatically cleared when a transmit complete interrupt is executed, or it can be cleared by
writing a one to its bit location. The TXCn Flag can generate a Transmit Complete interrupt
(see description of the TXCIEn bit).
• Bit 5 – UDREn: USART Data Register Empty
The UDREn Flag indicates if the transmit buffer (UDRn) is ready to receive new data. If
UDREn is one, the buffer is empty, and therefore ready to be written. The UDREn Flag can
generate a Data Register Empty interrupt (see description of the UDRIE bit). UDREn is set
after a reset to indicate that the Transmitter is ready.
• Bit 4:0 – Reserved Bits in MSPI mode
When in MSPI mode, these bits are reserved for future use. For compatibility with future
devices, these bits must be written to zero when UCSRnA is written.
• Bit 7 – RXCIEn: RX Complete Interrupt Enable
Writing this bit to one enables interrupt on the RXCn Flag. A USART Receive Complete inter-
rupt will be generated only if the RXCIEn bit is written to one, the Global Interrupt Flag in
SREG is written to one and the RXCn bit in UCSRnA is set.
Bit
Read/Write
Initial Value
Bit
Read/Write
Initial Value
Atmel ATmega48PA/88PA/168PA [Preliminary]
RXCn
R
7
0
RXCIEn
R/W
7
0
TXCn
R/W
6
0
TXCIEn
R/W
6
0
UDREn
R
5
0
UDRIE
R/W
5
0
R
4
–
0
RXENn
R/W
4
0
R
3
–
0
TXENn
R/W
3
0
R
2
–
1
R
2
–
1
1
–
R
1
R
1
1
-
R
0
–
0
R
0
0
-
UCSRnB
UCSRnA
209