ATmega48PA Automotive Atmel Corporation, ATmega48PA Automotive Datasheet - Page 158
ATmega48PA Automotive
Manufacturer Part Number
ATmega48PA Automotive
Description
Manufacturer
Atmel Corporation
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18.11 Register Description
18.11.1
158
Atmel ATmega48PA/88PA/168PA [Preliminary]
TCCR2A – Timer/Counter Control Register A
• Bits 7:6 – COM2A1:0: Compare Match Output A Mode
These bits control the Output Compare pin (OC2A) behavior. If one or both of the COM2A1:0
bits are set, the OC2A output overrides the normal port functionality of the I/O pin it is con-
nected to. However, note that the Data Direction Register (DDR) bit corresponding to the
OC2A pin must be set in order to enable the output driver.
When OC2A is connected to the pin, the function of the COM2A1:0 bits depends on the
WGM22:0 bit setting.
bits are set to a normal or CTC mode (non-PWM).
Table 18-2.
Table 18-3
mode.
Table 18-3.
Note:
Bit
(0xB0)
Read/Write
Initial Value
COM2A1
COM2A1
0
0
1
1
0
0
1
1
1. A special case occurs when OCR2A equals TOP and COM2A1 is set. In this case, the Com-
shows the COM2A1:0 bit functionality when the WGM21:0 bits are set to fast PWM
pare Match is ignored, but the set or clear is done at BOTTOM. See
page 150
COM2A1
Compare Output Mode, non-PWM Mode
Compare Output Mode, Fast PWM Mode
R/W
7
0
COM2A0
COM2A0
for more details.
0
1
0
1
0
1
0
1
Table 18-2
COM2A0
R/W
6
0
Description
Normal port operation, OC0A disconnected.
Toggle OC2A on Compare Match
Clear OC2A on Compare Match
Set OC2A on Compare Match
Description
Normal port operation, OC2A disconnected.
WGM22 = 0: Normal Port Operation, OC0A Disconnected.
WGM22 = 1: Toggle OC2A on Compare Match.
Clear OC2A on Compare Match, set OC2A at BOTTOM,
(non-inverting mode).
Set OC2A on Compare Match, clear OC2A at BOTTOM,
(inverting mode).
COM2B1
shows the COM2A1:0 bit functionality when the WGM22:0
R/W
5
0
COM2B0
R/W
4
0
R
3
–
0
(1)
R
2
–
0
WGM21
R/W
1
0
“Fast PWM Mode” on
WGM20
R/W
0
0
9223B–AVR–09/11
TCCR2A
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