AT32UC3C1512C Automotive Atmel Corporation, AT32UC3C1512C Automotive Datasheet - Page 311
AT32UC3C1512C Automotive
Manufacturer Part Number
AT32UC3C1512C Automotive
Description
Manufacturer
Atmel Corporation
Datasheets
1.AT90CAN128_AUTOMOTIVE.pdf
(225 pages)
2.AT32UC3C0512C_AUTOMOTIVE.pdf
(1312 pages)
3.AT32UC3C0512C_AUTOMOTIVE.pdf
(107 pages)
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18.6.4.1
9166C–AVR-08/11
Read waveforms
•NRD waveform
•NCS waveform
access type. NWR0 to NWR1 have the same timings and protocol as NWE. In the same way,
NCS represents one of the NCS[0..3] chip select lines.
The read cycle is shown on
The read cycle starts with the address setting on the memory address bus, i.e.:
Figure 18-7. Standard Read Cycle
The NRD signal is characterized by a setup timing, a pulse width, and a hold timing.
Similarly, the NCS signal can be divided into a setup time, pulse length and hold time.
NBS0, NBS1,
1. NRDSETUP: the NRD setup time is defined as the setup of address before the NRD
2. NRDPULSE: the NRD pulse length is the time between NRD falling edge and NRD ris-
3. NRDHOLD: the NRD hold time is defined as the hold time of address after the NRD ris-
A[AD_MSB:2]
A0, A1
falling edge.
ing edge.
ing edge.
{A[23:2], A1, A0} for 8-bit devices
{A[23:2], A1} for 16-bit devices
D[15:0]
CLK_SMC
NRD
NCS
NCSRDSETUP
NRDSETUP
Figure 18-7 on page
NCSRDPULSE
NRDPULSE
NRDCYCLE
311.
NRDHOLD
AT32UC3C
NCSRDHOLD
311
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