SAM9X35 Atmel Corporation, SAM9X35 Datasheet - Page 966

• Manufacturer Part Number: SAM9X35
• Manufacturer: Atmel Corporation

Specifications of SAM9X35

• Flash (kbytes): 0 Kbytes
• Pin Count: 217
• Max. Operating Frequency: 400 MHz
• Cpu: ARM926
• Hardware Qtouch Acquisition: No
• Max I/o Pins: 105
• Ext Interrupts: 105
• Usb Transceiver: 3
• Usb Speed: Hi-Speed
• Usb Interface: Host, Device
• Spi: 2
• Twi (i2c): 3
• Uart: 7
• Can: 2
• Lin: 4
• Ssc: 1
• Ethernet: 1
• Sd / Emmc: 2
• Graphic Lcd: Yes
• Video Decoder: No
• Camera Interface: No
• Adc Channels: 12
• Adc Resolution (bits): 10
• Adc Speed (ksps): 440
• Resistive Touch Screen: Yes
• Temp. Sensor: No
• Crypto Engine: No
• Sram (kbytes): 32
• Self Program Memory: NO
• External Bus Interface: 1
• Dram Memory: DDR/LPDDR, SDRAM/LPSDR
• Nand Interface: Yes
• Picopower: No
• Temp. Range (deg C): -40 to 85
• I/o Supply Class: 1.8/3.3
• Operating Voltage (vcc): 0.9 to 1.1
• Fpu: No
• Mpu / Mmu: No/Yes
• Timers: 6
• Output Compare Channels: 6
• Input Capture Channels: 6
• Pwm Channels: 4
• 32khz Rtc: Yes
• Calibrated Rc Oscillator: No

Figure 42-2. Sequence of ADC conversions
42.6.2
42.6.3
42.6.4
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(Hard or Soft)
Trigger event
ADC_Start
ADCClock
ADC_SEL
ADC_ON
ADC_eoc
SAM9X25
SAM9X25
Conversion Reference
Conversion Resolution
Conversion Results
DRDY
LCDR
The conversion is performed on a full range between 0V and the reference voltage pin ADVREF.
Analog inputs between these voltages convert to values based on a linear conversion.
The ADC supports 8-bit or 10-bit resolutions. The 8-bit selection is performed by setting the
LOWRES bit in the ADC Mode Register (ADC_MR). By default, after a reset, the resolution is
the highest and the DATA field in the data registers is fully used. By setting the LOWRES bit, the
ADC switches to the lowest resolution and the conversion results can be read in the lowest sig-
nificant bits of the data registers. The two highest bits of the DATA field in the corresponding
ADC_CDR register and of the LDATA field in the ADC_LCDR register read 0.
When a conversion is completed, the resulting 10-bit digital value is stored in the Channel Data
Register (ADC_CDRx) of the current channel and in the ADC Last Converted Data Register
(ADC_LCDR). By setting the TAG option in the ADC_EMR, the ADC_LCDR presents the chan-
nel number associated to the last converted data in the CHNB field.
The channel EOC bit in the Status Register (ADC_SR) is set and the DRDY is set. In the case of
a connected DMA channel, DRDY rising triggers a data transfer request. In any case, either
EOC and DRDY can trigger an interrupt.
Reading one of the ADC_CDR registers clears the corresponding EOC bit. Reading ADC_LCDR
clears the DRDY bit and EOC bit corresponding to the last converted channel.
(and tracking of CH0)
CH0
Start Up Time
Conversion of CH0
CH0
CH1
Tracking of CH1
Conversion of CH1
CH2
CH1
Tracking of CH2
11054A–ATARM–27-Jul-11
11054A–ATARM–27-Jul-11