SAM9X35 Atmel Corporation, SAM9X35 Datasheet - Page 944

• Manufacturer Part Number: SAM9X35
• Manufacturer: Atmel Corporation

Specifications of SAM9X35

• Flash (kbytes): 0 Kbytes
• Pin Count: 217
• Max. Operating Frequency: 400 MHz
• Cpu: ARM926
• Hardware Qtouch Acquisition: No
• Max I/o Pins: 105
• Ext Interrupts: 105
• Usb Transceiver: 3
• Usb Speed: Hi-Speed
• Usb Interface: Host, Device
• Spi: 2
• Twi (i2c): 3
• Uart: 7
• Can: 2
• Lin: 4
• Ssc: 1
• Ethernet: 1
• Sd / Emmc: 2
• Graphic Lcd: Yes
• Video Decoder: No
• Camera Interface: No
• Adc Channels: 12
• Adc Resolution (bits): 10
• Adc Speed (ksps): 440
• Resistive Touch Screen: Yes
• Temp. Sensor: No
• Crypto Engine: No
• Sram (kbytes): 32
• Self Program Memory: NO
• External Bus Interface: 1
• Dram Memory: DDR/LPDDR, SDRAM/LPSDR
• Nand Interface: Yes
• Picopower: No
• Temp. Range (deg C): -40 to 85
• I/o Supply Class: 1.8/3.3
• Operating Voltage (vcc): 0.9 to 1.1
• Fpu: No
• Mpu / Mmu: No/Yes
• Timers: 6
• Output Compare Channels: 6
• Input Capture Channels: 6
• Pwm Channels: 4
• 32khz Rtc: Yes
• Calibrated Rc Oscillator: No

41.9.6
Name:
Address:
Access:
Any modification on one of the fields of the CANBR register must be done while CAN module is disabled.
To compute the different Bit Timings, please refer to the
• PHASE2: Phase 2 segment
This phase is used to compensate the edge phase error.
Warning: PHASE2 value must be different from 0.
• PHASE1: Phase 1 segment
This phase is used to compensate for edge phase error.
• PROPAG: Programming time segment
This part of the bit time is used to compensate for the physical delay times within the network.
• SJW: Re-synchronization jump width
To compensate for phase shifts between clock oscillators of different controllers on bus. The controller must re-synchronize
on any relevant signal edge of the current transmission. The synchronization jump width defines the maximum of clock
cycles a bit period may be shortened or lengthened by re-synchronization.
• BRP: Baudrate Prescaler.
This field allows user to program the period of the CAN system clock to determine the individual bit timing.
The BRP field must be within the range [1, 0x7F], i.e., BRP = 0 is not authorized.
• SMP: Sampling Mode
0 = The incoming bit stream is sampled once at sample point.
1 = The incoming bit stream is sampled three times with a period of a MCK clock period, centered on sample point.
SMP Sampling Mode is automatically disabled if BRP = 0.
944
944
31
23
15
–
–
–
7
–
SAM9X25
SAM9X25
CAN Baudrate Register
t
t
t
t
t
PHS2
PHS1
PRS
SJW
CSC
=
=
=
=
=
30
22
14
CAN_BR
0xF8000014 (0), 0xF8004014 (1)
Read-write
–
–
6
t
t
CSC
CSC
t
t
BRP
CSC
CSC
+
1
PROPAG
SJW
PHASE2
PHASE1
PHASE1
MCK
+
29
21
13
–
5
1
+
+
+
1
1
1
SJW
28
20
12
–
4
Section 41.7.4.1 “CAN Bit Timing Configuration” on page
BRP
27
19
11
–
–
3
–
26
18
10
–
2
PROPAG
PHASE2
25
17
–
9
1
11054A–ATARM–27-Jul-11
11054A–ATARM–27-Jul-11
SMP
24
16
912.
8
0