SAM9X35 Atmel Corporation, SAM9X35 Datasheet - Page 227
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SAM9X35
Manufacturer Part Number
SAM9X35
Description
Manufacturer
Atmel Corporation
Datasheets
1.SAM9261.pdf
(248 pages)
2.SAM9X25.pdf
(45 pages)
3.SAM9X25.pdf
(1145 pages)
4.SAM9X25.pdf
(45 pages)
5.SAM9X25.pdf
(1325 pages)
Specifications of SAM9X35
Flash (kbytes)
0 Kbytes
Pin Count
217
Max. Operating Frequency
400 MHz
Cpu
ARM926
Hardware Qtouch Acquisition
No
Max I/o Pins
105
Ext Interrupts
105
Usb Transceiver
3
Usb Speed
Hi-Speed
Usb Interface
Host, Device
Spi
2
Twi (i2c)
3
Uart
7
Can
2
Lin
4
Ssc
1
Ethernet
1
Sd / Emmc
2
Graphic Lcd
Yes
Video Decoder
No
Camera Interface
No
Adc Channels
12
Adc Resolution (bits)
10
Adc Speed (ksps)
440
Resistive Touch Screen
Yes
Temp. Sensor
No
Crypto Engine
No
Sram (kbytes)
32
Self Program Memory
NO
External Bus Interface
1
Dram Memory
DDR/LPDDR, SDRAM/LPSDR
Nand Interface
Yes
Picopower
No
Temp. Range (deg C)
-40 to 85
I/o Supply Class
1.8/3.3
Operating Voltage (vcc)
0.9 to 1.1
Fpu
No
Mpu / Mmu
No/Yes
Timers
6
Output Compare Channels
6
Input Capture Channels
6
Pwm Channels
4
32khz Rtc
Yes
Calibrated Rc Oscillator
No
- SAM9261 PDF datasheet
- SAM9X25 PDF datasheet #2
- SAM9X25 PDF datasheet #3
- SAM9X25 PDF datasheet #4
- SAM9X25 PDF datasheet #5
- Current page: 227 of 1145
- Download datasheet (26Mb)
23.5.10.2
23.5.10.3
23.5.10.4
Figure 23-8. Input Change Interrupt Timings if there are no Additional Interrupt Modes
23.5.11
23.5.12
11054A–ATARM–27-Jul-11
11054A–ATARM–27-Jul-11
Read PIO_ISR
Pin Level
PIO_ISR
MCK
I/O Lines Lock
Programmable I/O Delays
Interrupt Mode Configuration
Edge or Level Detection Configuration
Falling/Rising Edge or Low/High Level Detection Configuration.
All the interrupt sources are enabled by writing 32’hFFFF_FFFF in PIO_IER.
Then the Additional Interrupt Mode is enabled for line 0 to 7 by writing 32’h0000_00FF in
PIO_AIMER.
Lines 3, 4 and 5 are configured in Level detection by writing 32’h0000_0038 in PIO_LSR.
The other lines are configured in Edge detection by default, if they have not been previously con-
figured. Otherwise, lines 0, 1, 2, 6 and 7 must be configured in Edge detection by writing
32’h0000_00C7 in PIO_ESR.
Lines 0, 2, 4, 5 and 7 are configured in Rising Edge or High Level detection by writing
32’h0000_00B5 in PIO_REHLSR.
The other lines are configured in Falling Edge or Low Level detection by default, if they have not
been previously configured. Otherwise, lines 1, 3 and 6 must be configured in Falling Edge/Low
Level detection by writing 32’h0000_004A in PIO_FELLSR.
When an I/O line is controlled by a peripheral (particularly the Pulse Width Modulation Controller
PWM), it can become locked by the action of this peripheral via an input of the PIO controller.
When an I/O line is locked, the write of the corresponding bit in the registers PIO_PER,
PIO_PDR, PIO_MDER, PIO_MDDR, PIO_PUDR, PIO_PUER, PIO_ABCDSR1 and
PIO_ABCDSR2 is discarded in order to lock its configuration. The user can know at anytime
which I/O line is locked by reading the PIO Lock Status register PIO_LOCKSR. Once an I/O line
is locked, the only way to unlock it is to apply a hardware reset to the PIO Controller.
The PIO interface consists of a series of signals driven by peripherals or directly by software.
The simultaneous switching outputs on these busses may lead to a peak of current in the inter-
nal and external power supply lines.
In order to reduce the current peak in such cases, additional propagation delays can be adjusted
independently for pad buffers by means of configuration registers, PIO_DELAY.
APB Access
APB Access
SAM9X25
SAM9X25
227
227
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