SAM9X35 Atmel Corporation, SAM9X35 Datasheet - Page 194
![no-image](/images/manufacturer_photos/0/0/79/atmel_corporation_sml.jpg)
SAM9X35
Manufacturer Part Number
SAM9X35
Description
Manufacturer
Atmel Corporation
Datasheets
1.SAM9261.pdf
(248 pages)
2.SAM9X25.pdf
(45 pages)
3.SAM9X25.pdf
(1145 pages)
4.SAM9X25.pdf
(45 pages)
5.SAM9X25.pdf
(1325 pages)
Specifications of SAM9X35
Flash (kbytes)
0 Kbytes
Pin Count
217
Max. Operating Frequency
400 MHz
Cpu
ARM926
Hardware Qtouch Acquisition
No
Max I/o Pins
105
Ext Interrupts
105
Usb Transceiver
3
Usb Speed
Hi-Speed
Usb Interface
Host, Device
Spi
2
Twi (i2c)
3
Uart
7
Can
2
Lin
4
Ssc
1
Ethernet
1
Sd / Emmc
2
Graphic Lcd
Yes
Video Decoder
No
Camera Interface
No
Adc Channels
12
Adc Resolution (bits)
10
Adc Speed (ksps)
440
Resistive Touch Screen
Yes
Temp. Sensor
No
Crypto Engine
No
Sram (kbytes)
32
Self Program Memory
NO
External Bus Interface
1
Dram Memory
DDR/LPDDR, SDRAM/LPSDR
Nand Interface
Yes
Picopower
No
Temp. Range (deg C)
-40 to 85
I/o Supply Class
1.8/3.3
Operating Voltage (vcc)
0.9 to 1.1
Fpu
No
Mpu / Mmu
No/Yes
Timers
6
Output Compare Channels
6
Input Capture Channels
6
Pwm Channels
4
32khz Rtc
Yes
Calibrated Rc Oscillator
No
- SAM9261 PDF datasheet
- SAM9X25 PDF datasheet #2
- SAM9X25 PDF datasheet #3
- SAM9X25 PDF datasheet #4
- SAM9X25 PDF datasheet #5
- Current page: 194 of 1145
- Download datasheet (26Mb)
22.13.3
Name:
Address:
Access:
• PCK: Processor Clock Status
0 = The Processor clock is disabled.
1 = The Processor clock is enabled.
• DDRCK: DDR Clock Status
0 = The DDR clock is disabled.
1 = The DDR clock is enabled.
• SMDCK: SMD Clock Status
0 = The soft modem clock is disabled.
1 = The soft modem clock is enabled.
• UHP: USB Host Port Clock Status
0 = The UHP48M and UHP12M OHCI clocks are disabled.
1 = The UHP48M and UHP12M OHCI clocks are enabled.
• UDP: USB Device Port Clock Status
0 = The USB Device clock is disabled.
1 = The USB Device clock is enabled.
• PCKx: Programmable Clock x Output Status
0 = The corresponding Programmable Clock output is disabled.
1 = The corresponding Programmable Clock output is enabled.
194
194
UDP
31
23
15
–
–
–
7
SAM9X25
SAM9X25
PMC System Clock Status Register
UHP
30
22
14
PMC_SCSR
0xFFFFFC08
Read-only
–
–
–
6
29
21
13
–
–
–
5
–
SMDCK
28
20
12
–
–
–
4
27
19
11
–
–
–
–
3
DDRCK
26
18
10
–
–
–
2
PCK1
25
17
–
–
–
9
1
11054A–ATARM–27-Jul-11
11054A–ATARM–27-Jul-11
PCK0
PCK
24
16
–
–
8
0
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