SAM9X35 Atmel Corporation, SAM9X35 Datasheet - Page 313
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SAM9X35
Manufacturer Part Number
SAM9X35
Description
Manufacturer
Atmel Corporation
Datasheets
1.SAM9261.pdf
(248 pages)
2.SAM9X25.pdf
(45 pages)
3.SAM9X25.pdf
(1145 pages)
4.SAM9X25.pdf
(45 pages)
5.SAM9X25.pdf
(1325 pages)
Specifications of SAM9X35
Flash (kbytes)
0 Kbytes
Pin Count
217
Max. Operating Frequency
400 MHz
Cpu
ARM926
Hardware Qtouch Acquisition
No
Max I/o Pins
105
Ext Interrupts
105
Usb Transceiver
3
Usb Speed
Hi-Speed
Usb Interface
Host, Device
Spi
2
Twi (i2c)
3
Uart
7
Can
2
Lin
4
Ssc
1
Ethernet
1
Sd / Emmc
2
Graphic Lcd
Yes
Video Decoder
No
Camera Interface
No
Adc Channels
12
Adc Resolution (bits)
10
Adc Speed (ksps)
440
Resistive Touch Screen
Yes
Temp. Sensor
No
Crypto Engine
No
Sram (kbytes)
32
Self Program Memory
NO
External Bus Interface
1
Dram Memory
DDR/LPDDR, SDRAM/LPSDR
Nand Interface
Yes
Picopower
No
Temp. Range (deg C)
-40 to 85
I/o Supply Class
1.8/3.3
Operating Voltage (vcc)
0.9 to 1.1
Fpu
No
Mpu / Mmu
No/Yes
Timers
6
Output Compare Channels
6
Input Capture Channels
6
Pwm Channels
4
32khz Rtc
Yes
Calibrated Rc Oscillator
No
- SAM9261 PDF datasheet
- SAM9X25 PDF datasheet #2
- SAM9X25 PDF datasheet #3
- SAM9X25 PDF datasheet #4
- SAM9X25 PDF datasheet #5
- Current page: 313 of 1145
- Download datasheet (26Mb)
26.4
Table 26-1.
11054A–ATARM–27-Jul-11
11054A–ATARM–27-Jul-11
Name
EBI_D0 - EBI_D31
EBI_A0 - EBI_A25
EBI_NWAIT
EBI_NCS0 - EBI_NCS5
EBI_NWR0 - EBI_NWR3
EBI_NRD
EBI_NWE
EBI_NBS0 - EBI_NBS3
EBI_NANDCS
EBI_NANDOE
EBI_NANDWE
EBI_SDCK, EBI_SDCK#
EBI_SDCKE
EBI_SDCS
EBI_BA0 - 2
EBI_SDWE
EBI_RAS - EBI_CAS
EBI_SDA10
I/O Lines Description
EBI I/O Lines Description
The connection of some signals through the MUX logic is not direct and depends on the Memory
Controller in use at the moment.
Table 26-2 on page 313
EBI pins.
Table 26-2.
EBI_NWR1/NBS1/CFIOR
EBI_A0/NBS0
EBI_A1/NBS2/NWR2
EBI_A[11:2]
EBI_SDA10
EBI_A12
EBI_A[14:13]
EBI_A[25:15]
EBI_D[31:0]
Chip Select Lines
Read Signal
NAND Flash Chip Select Line
NAND Flash Output Enable
NAND Flash Write Enable
DDR2/SDRAM Differential Clock
DDR2/SDRAM Clock Enable
SDRAM Address 10 Line
Function
Data Bus
Address Bus
External Wait Signal
Write Signals
Write Enable
Byte Mask Signals
DDR2/SDRAM Controller Chip Select Line
Bank Select
DDR2/SDRAM Write Enable
Row and Column Signal
EBI Pins and Memory Controllers I/O Lines Connections
EBIx Pins
EBI for NAND Flash Support
DDR2/SDRAM Controller
details the connections between the two Memory Controllers and the
SMC
EBI
NBS1
Not Supported
Not Supported
SDRAMC_A[9:0]
SDRAMC_A10
Not Supported
SDRAMC_A[12:11]
Not Supported
D[31:0]
SDRAM I/O Lines
Output
Output
Output
Output
Output
Output
Output
Output
Output
Output
Output
Output
Output
Output
Output
Output
Type
Input
I/O
NWR1
SMC_A0
SMC_A1
SMC_A[11:2]
Not Supported
SMC_A12
SMC_A[14:13]
SMC_A[25:15]
D[31:0]
SMC I/O Lines
SAM9X25
SAM9X25
Active Level
High
Low
Low
Low
Low
Low
Low
Low
Low
Low
Low
Low
Low
313
313
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