SAM9X35 Atmel Corporation, SAM9X35 Datasheet - Page 501
SAM9X35
Manufacturer Part Number
SAM9X35
Description
Manufacturer
Atmel Corporation
Datasheets
1.SAM9261.pdf
(248 pages)
2.SAM9X25.pdf
(45 pages)
3.SAM9X25.pdf
(1145 pages)
4.SAM9X25.pdf
(45 pages)
5.SAM9X25.pdf
(1325 pages)
Specifications of SAM9X35
Flash (kbytes)
0 Kbytes
Pin Count
217
Max. Operating Frequency
400 MHz
Cpu
ARM926
Hardware Qtouch Acquisition
No
Max I/o Pins
105
Ext Interrupts
105
Usb Transceiver
3
Usb Speed
Hi-Speed
Usb Interface
Host, Device
Spi
2
Twi (i2c)
3
Uart
7
Can
2
Lin
4
Ssc
1
Ethernet
1
Sd / Emmc
2
Graphic Lcd
Yes
Video Decoder
No
Camera Interface
No
Adc Channels
12
Adc Resolution (bits)
10
Adc Speed (ksps)
440
Resistive Touch Screen
Yes
Temp. Sensor
No
Crypto Engine
No
Sram (kbytes)
32
Self Program Memory
NO
External Bus Interface
1
Dram Memory
DDR/LPDDR, SDRAM/LPSDR
Nand Interface
Yes
Picopower
No
Temp. Range (deg C)
-40 to 85
I/o Supply Class
1.8/3.3
Operating Voltage (vcc)
0.9 to 1.1
Fpu
No
Mpu / Mmu
No/Yes
Timers
6
Output Compare Channels
6
Input Capture Channels
6
Pwm Channels
4
32khz Rtc
Yes
Calibrated Rc Oscillator
No
- SAM9261 PDF datasheet
- SAM9X25 PDF datasheet #2
- SAM9X25 PDF datasheet #3
- SAM9X25 PDF datasheet #4
- SAM9X25 PDF datasheet #5
- Current page: 501 of 1145
- Download datasheet (26Mb)
31.6
11054A–ATARM–27-Jul-11
11054A–ATARM–27-Jul-11
Write Protection Registers
To prevent any single software error that may corrupt DMAC behavior, the DMAC address
space can be write-protected by setting the WPEN bit in the
ter”
If a write access to anywhere in the DMAC address space is detected, then the WPVS flag in the
DMAC Write Protect Status Register (MCI_WPSR) is set and the field WPVSRC indicates in
which register the write access has been attempted.
The WPVS flag is reset by writing the DMAC Write Protect Mode Register (DMAC_WPMR) with
the appropriate access key, WPKEY.
The protected registers are:
•
•
•
•
•
•
•
•
•
•
“DMAC Global Configuration Register” on page 503
“DMAC Enable Register” on page 504
“DMAC Channel x [x = 0..7] Source Address Register” on page 514
“DMAC Channel x [x = 0..7] Destination Address Register” on page 515
“DMAC Channel x [x = 0..7] Descriptor Address Register” on page 516
“DMAC Channel x [x = 0..7] Control A Register” on page 517
“DMAC Channel x [x = 0..7] Control B Register” on page 519
“DMAC Channel x [x = 0..7] Configuration Register” on page 521
“DMAC Channel x [x = 0..7] Source Picture in Picture Configuration Register” on page 523
“DMAC Channel x [x = 0..7] Destination Picture in Picture Configuration Register” on page
524
(DMAC_WPMR).
“DMAC Write Protect Mode Regis-
SAM9X25
SAM9X25
501
501
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