SAM9X35 Atmel Corporation, SAM9X35 Datasheet - Page 434
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SAM9X35
Manufacturer Part Number
SAM9X35
Description
Manufacturer
Atmel Corporation
Datasheets
1.SAM9261.pdf
(248 pages)
2.SAM9X25.pdf
(45 pages)
3.SAM9X25.pdf
(1145 pages)
4.SAM9X25.pdf
(45 pages)
5.SAM9X25.pdf
(1325 pages)
Specifications of SAM9X35
Flash (kbytes)
0 Kbytes
Pin Count
217
Max. Operating Frequency
400 MHz
Cpu
ARM926
Hardware Qtouch Acquisition
No
Max I/o Pins
105
Ext Interrupts
105
Usb Transceiver
3
Usb Speed
Hi-Speed
Usb Interface
Host, Device
Spi
2
Twi (i2c)
3
Uart
7
Can
2
Lin
4
Ssc
1
Ethernet
1
Sd / Emmc
2
Graphic Lcd
Yes
Video Decoder
No
Camera Interface
No
Adc Channels
12
Adc Resolution (bits)
10
Adc Speed (ksps)
440
Resistive Touch Screen
Yes
Temp. Sensor
No
Crypto Engine
No
Sram (kbytes)
32
Self Program Memory
NO
External Bus Interface
1
Dram Memory
DDR/LPDDR, SDRAM/LPSDR
Nand Interface
Yes
Picopower
No
Temp. Range (deg C)
-40 to 85
I/o Supply Class
1.8/3.3
Operating Voltage (vcc)
0.9 to 1.1
Fpu
No
Mpu / Mmu
No/Yes
Timers
6
Output Compare Channels
6
Input Capture Channels
6
Pwm Channels
4
32khz Rtc
Yes
Calibrated Rc Oscillator
No
- SAM9261 PDF datasheet
- SAM9X25 PDF datasheet #2
- SAM9X25 PDF datasheet #3
- SAM9X25 PDF datasheet #4
- SAM9X25 PDF datasheet #5
- Current page: 434 of 1145
- Download datasheet (26Mb)
Figure 30-10. SINGLE Write Access Followed By A Read Access, DDR2 -SDRAM Device
30.5.2
434
434
COMMAND
DQS[1:0]
DM[1:0]
SAM9X25
SAM9X25
SDCLK
BA[1:0]
D[15:0]
A[12:0]
SDRAM Controller Read Cycle
NOP PRCHG NOP
0
3
The DDRSDRC allows burst access or single access in normal mode (mode =000). Whatever
access type, the DDRSDRC keeps track of the active row in each bank, thus maximizing perfor-
mance of the DDRSDRC.
The SDRAM devices are programmed with a burst length equal to 8 which determines the length
of a sequential data output by the read command that is set to 8. The latency from read com-
mand to data output is equal to 2 or 3. This value is programmed during the initialization phase
(see
To initiate a single access, the DDRSDRC checks if the page access is already open. If
row/bank addresses match with the previous row/bank addresses, the controller generates a
read command. If the bank addresses are not identical or if bank addresses are identical but the
row addresses are not identical, the controller generates a precharge command, activates the
new row and initiates a read command. To comply with SDRAM timing parameters, additional
clock cycles are inserted between precharge/active (Trp) commands and active/read (Trcd)
command. After a read command, additional wait states are generated to comply with cas
latency. The DDRSDRC supports a cas latency of two, two and half, and three (2 or 3 clocks
delay). As the burst length is fixed to 8, in the case of single access or burst access inferior to 8
data requests, it has to stop the burst otherwise seven or X values could be read. Burst Stop
Command (BST) is used to stop output during a burst read.
To initiate a burst access, the DDRSDRC checks the transfer type signal. If the next accesses
are sequential read accesses, reading to the SDRAM device is carried out. If the next access is
a read non-sequential access, then an automatic page break can be inserted. If the bank
addresses are not identical or if bank addresses are identical but the row addresses are not
identical, the controller generates a precharge command, activates the new row and initiates a
read command. In the case where the page access is already open, a read command is
generated.
Row a
Section 30.4.1 “SDR-SDRAM Initialization” on page
ACT
NOP WRITE
col a
NOP
Da
0
Db
3
Data masked
twtr
424).
READ
NOP
11054A–ATARM–27-Jul-11
11054A–ATARM–27-Jul-11
Da Db
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