SAM9X35 Atmel Corporation, SAM9X35 Datasheet - Page 462
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SAM9X35
Manufacturer Part Number
SAM9X35
Description
Manufacturer
Atmel Corporation
Datasheets
1.SAM9261.pdf
(248 pages)
2.SAM9X25.pdf
(45 pages)
3.SAM9X25.pdf
(1145 pages)
4.SAM9X25.pdf
(45 pages)
5.SAM9X25.pdf
(1325 pages)
Specifications of SAM9X35
Flash (kbytes)
0 Kbytes
Pin Count
217
Max. Operating Frequency
400 MHz
Cpu
ARM926
Hardware Qtouch Acquisition
No
Max I/o Pins
105
Ext Interrupts
105
Usb Transceiver
3
Usb Speed
Hi-Speed
Usb Interface
Host, Device
Spi
2
Twi (i2c)
3
Uart
7
Can
2
Lin
4
Ssc
1
Ethernet
1
Sd / Emmc
2
Graphic Lcd
Yes
Video Decoder
No
Camera Interface
No
Adc Channels
12
Adc Resolution (bits)
10
Adc Speed (ksps)
440
Resistive Touch Screen
Yes
Temp. Sensor
No
Crypto Engine
No
Sram (kbytes)
32
Self Program Memory
NO
External Bus Interface
1
Dram Memory
DDR/LPDDR, SDRAM/LPSDR
Nand Interface
Yes
Picopower
No
Temp. Range (deg C)
-40 to 85
I/o Supply Class
1.8/3.3
Operating Voltage (vcc)
0.9 to 1.1
Fpu
No
Mpu / Mmu
No/Yes
Timers
6
Output Compare Channels
6
Input Capture Channels
6
Pwm Channels
4
32khz Rtc
Yes
Calibrated Rc Oscillator
No
- SAM9261 PDF datasheet
- SAM9X25 PDF datasheet #2
- SAM9X25 PDF datasheet #3
- SAM9X25 PDF datasheet #4
- SAM9X25 PDF datasheet #5
- Current page: 462 of 1145
- Download datasheet (26Mb)
• DS: Drive Strength
Reset value is “0”.
This field is unique to Low-power SDRAM. It selects the driver strength of SDRAM output.
After the initialization sequence, as soon as DS field is modified, Extended Mode Register is accessed automatically and
DS bits are updated. In function of UPD_MR bit, update is done before entering in self refresh mode or during a refresh
command and a pending read or write access.
• TIMEOUT: Low Power Mode
Reset value is “00”.
This field defines when low-power mode is enabled.
• APDE: Active Power Down Exit Time
Reset value is “1”.
This mode is unique to DDR2-SDRAM devices. This mode allows to determine the active power-down mode, which
determines performance versus power saving.
0 = Fast Exit
1 = Slow Exit
After the initialization sequence, as soon as APDE field is modified Extended Mode Register, located in the memory of the
external device, is accessed automatically and APDE bits are updated. In function of the UPD_MR bit, update is done
before entering in self refresh mode or during a refresh command and a pending read or write access
• UPD_MR: Update Load Mode Register and Extended Mode Register
Reset value is “0”.
This bit is used to enable or disable automatic update of the Load Mode Register and Extended Mode Register. This
update is function of DDRSDRC integration in a system. DDRSDRC can either share or not share an external bus with
another controller.
462
462
00
01
10
11
00
01
10
11
SAM9X25
SAM9X25
The SDRAM controller activates the SDRAM low-power mode immediately after the end of the last transfer.
The SDRAM controller activates the SDRAM low-power mode 64 clock cycles after the end of the last transfer.
The SDRAM controller activates the SDRAM low-power mode 128 clock cycles after the end of the last transfer.
Reserved
Update is disabled.
DDRSDRC shares external bus. Automatic update is done during a refresh command and a pending read or write
access in SDRAM device.
DDRSDRC does not share external bus. Automatic update is done before entering in self refresh mode.
Reserved
11054A–ATARM–27-Jul-11
11054A–ATARM–27-Jul-11
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