SAM9X35 Atmel Corporation, SAM9X35 Datasheet - Page 188
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SAM9X35
Manufacturer Part Number
SAM9X35
Description
Manufacturer
Atmel Corporation
Datasheets
1.SAM9261.pdf
(248 pages)
2.SAM9X25.pdf
(45 pages)
3.SAM9X25.pdf
(1145 pages)
4.SAM9X25.pdf
(45 pages)
5.SAM9X25.pdf
(1325 pages)
Specifications of SAM9X35
Flash (kbytes)
0 Kbytes
Pin Count
217
Max. Operating Frequency
400 MHz
Cpu
ARM926
Hardware Qtouch Acquisition
No
Max I/o Pins
105
Ext Interrupts
105
Usb Transceiver
3
Usb Speed
Hi-Speed
Usb Interface
Host, Device
Spi
2
Twi (i2c)
3
Uart
7
Can
2
Lin
4
Ssc
1
Ethernet
1
Sd / Emmc
2
Graphic Lcd
Yes
Video Decoder
No
Camera Interface
No
Adc Channels
12
Adc Resolution (bits)
10
Adc Speed (ksps)
440
Resistive Touch Screen
Yes
Temp. Sensor
No
Crypto Engine
No
Sram (kbytes)
32
Self Program Memory
NO
External Bus Interface
1
Dram Memory
DDR/LPDDR, SDRAM/LPSDR
Nand Interface
Yes
Picopower
No
Temp. Range (deg C)
-40 to 85
I/o Supply Class
1.8/3.3
Operating Voltage (vcc)
0.9 to 1.1
Fpu
No
Mpu / Mmu
No/Yes
Timers
6
Output Compare Channels
6
Input Capture Channels
6
Pwm Channels
4
32khz Rtc
Yes
Calibrated Rc Oscillator
No
- SAM9261 PDF datasheet
- SAM9X25 PDF datasheet #2
- SAM9X25 PDF datasheet #3
- SAM9X25 PDF datasheet #4
- SAM9X25 PDF datasheet #5
- Current page: 188 of 1145
- Download datasheet (26Mb)
22.12 Clock Switching Details
22.12.1
188
188
SAM9X25
SAM9X25
Master Clock Switching Timings
Table 22-1
from one selected clock to another one. This is in the event that the prescaler is de-activated.
When the prescaler is activated, an additional time of 64 clock cycles of the new selected clock
has to be added.
Table 22-1.
Notes:
Table 22-2.
To
Main Clock
SLCK
PLL Clock
To
PLLA Clock
UPLL Clock
Peripheral clock 4 is disabled.
1. PLL designates either the PLLA or the UPLL Clock.
2. PLLCOUNT designates either PLLACOUNT or UPLLCOUNT.
and
From
Clock Switching Timings (Worst Case)
Clock Switching Timings between Two PLLs (Worst Case)
From
Table 22-2
PLLCOUNT x SLCK +
0.5 x Main Clock +
0.5 x Main Clock +
2.5 x PLLx Clock
Main Clock
give the worst case timings required for the Master Clock to switch
4.5 x SLCK
4 x SLCK +
PLLACOUNT x SLCK
2.5 x PLLA Clock +
3 x UPLL Clock +
1.5 x UPLL Clock
–
PLLA Clock
4 x SLCK +
4 x SLCK +
PLLCOUNT x SLCK
2.5 x PLL Clock +
2.5 x Main Clock
4 x SLCK +
5 x SLCK +
SLCK
–
UPLLCOUNT x SLCK
2.5 x UPLL Clock +
3 x PLLA Clock +
1.5 x PLLA Clock
UPLL Clock
4 x SLCK +
4 x SLCK +
PLLCOUNT x SLCK
2.5 x PLL Clock +
11054A–ATARM–27-Jul-11
11054A–ATARM–27-Jul-11
3 x PLL Clock +
3 x PLL Clock +
1 x Main Clock
4 x SLCK +
4 x SLCK +
PLL Clock
5 x SLCK
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