SAM9G15 Atmel Corporation, SAM9G15 Datasheet - Page 851
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SAM9G15
Manufacturer Part Number
SAM9G15
Description
Manufacturer
Atmel Corporation
Datasheets
1.SAM9261.pdf
(248 pages)
2.SAM9261.pdf
(1274 pages)
3.SAM9261.pdf
(43 pages)
4.SAM9G15.pdf
(1211 pages)
5.SAM9G15.pdf
(45 pages)
Specifications of SAM9G15
Flash (kbytes)
0 Kbytes
Pin Count
217
Max. Operating Frequency
400 MHz
Cpu
ARM926
Hardware Qtouch Acquisition
No
Max I/o Pins
105
Ext Interrupts
105
Usb Transceiver
3
Usb Speed
Hi-Speed
Usb Interface
Host, Device
Spi
2
Twi (i2c)
3
Uart
6
Lin
4
Ssc
1
Sd / Emmc
2
Graphic Lcd
Yes
Video Decoder
No
Camera Interface
No
Adc Channels
12
Adc Resolution (bits)
10
Adc Speed (ksps)
440
Resistive Touch Screen
Yes
Temp. Sensor
No
Crypto Engine
No
Sram (kbytes)
32
Self Program Memory
NO
External Bus Interface
1
Dram Memory
DDR2/LPDDR, SDRAM/LPSDR
Nand Interface
Yes
Picopower
No
Temp. Range (deg C)
-40 to 85
I/o Supply Class
1.8/3.3
Operating Voltage (vcc)
0.9 to 1.1
Fpu
No
Mpu / Mmu
No/Yes
Timers
6
Output Compare Channels
6
Input Capture Channels
6
Pwm Channels
4
32khz Rtc
Yes
Calibrated Rc Oscillator
No
- SAM9261 PDF datasheet
- SAM9261 PDF datasheet #2
- SAM9261 PDF datasheet #3
- SAM9G15 PDF datasheet #4
- SAM9G15 PDF datasheet #5
- Current page: 851 of 1211
- Download datasheet (25Mb)
Figure 39-51. Master Node with DMAC (PDCM = 1)
11052C–ATARM–21-Nov-11
WRITE BUFFER
Master Node Configuration
IDENTIFIER
CHKTYP
PARDIS
CHKDIS
DATA N
DATA 0
FSDIS
NACT
DLM
DLC
|
|
|
|
(Peripheral) DMA
Controller
The user can choose between two DMAC modes by the PDCM bit in the LIN Mode register
(US_LINMR):
The WRITE buffer also contains the Identifier and the DATA, if the USART sends the response
(NACT = PUBLISH).
The READ buffer contains the DATA if the USART receives the response (NACT =
SUBSCRIBE).
• PDCM = 1: the LIN configuration is stored in the WRITE buffer and it is written by the DMAC
• PDCM = 0: the LIN configuration is not stored in the WRITE buffer and it must be written by
in the Transmit Holding register US_THR (instead of the LIN Mode register US_LINMR).
Because the DMAC transfer size is limited to a byte, the transfer is split into two accesses.
During the first access the bits, NACT, PARDIS, CHKDIS, CHKTYP, DLM and FSDIS are
written. During the second access the 8-bit DLC field is written.
the user in the LIN Mode register (US_LINMR).
APB bus
TXRDY
NODE ACTION = PUBLISH
LIN CONTROLLER
USART3
WRITE BUFFER
READ BUFFER
IDENTIFIER
CHKTYP
CHKDIS
PARDIS
DATA N
DATA 0
FSDIS
NACT
DLM
DLC
|
|
|
|
(Peripheral) DMA
Controller
APB bus
RXRDY
TXRDY
NODE ACTION = SUBSCRIBE
SAM9G15
LIN CONTROLLER
USART3
851
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