SAM9G15 Atmel Corporation, SAM9G15 Datasheet - Page 1199
SAM9G15
Manufacturer Part Number
SAM9G15
Description
Manufacturer
Atmel Corporation
Datasheets
1.SAM9261.pdf
(248 pages)
2.SAM9261.pdf
(1274 pages)
3.SAM9261.pdf
(43 pages)
4.SAM9G15.pdf
(1211 pages)
5.SAM9G15.pdf
(45 pages)
Specifications of SAM9G15
Flash (kbytes)
0 Kbytes
Pin Count
217
Max. Operating Frequency
400 MHz
Cpu
ARM926
Hardware Qtouch Acquisition
No
Max I/o Pins
105
Ext Interrupts
105
Usb Transceiver
3
Usb Speed
Hi-Speed
Usb Interface
Host, Device
Spi
2
Twi (i2c)
3
Uart
6
Lin
4
Ssc
1
Sd / Emmc
2
Graphic Lcd
Yes
Video Decoder
No
Camera Interface
No
Adc Channels
12
Adc Resolution (bits)
10
Adc Speed (ksps)
440
Resistive Touch Screen
Yes
Temp. Sensor
No
Crypto Engine
No
Sram (kbytes)
32
Self Program Memory
NO
External Bus Interface
1
Dram Memory
DDR2/LPDDR, SDRAM/LPSDR
Nand Interface
Yes
Picopower
No
Temp. Range (deg C)
-40 to 85
I/o Supply Class
1.8/3.3
Operating Voltage (vcc)
0.9 to 1.1
Fpu
No
Mpu / Mmu
No/Yes
Timers
6
Output Compare Channels
6
Input Capture Channels
6
Pwm Channels
4
32khz Rtc
Yes
Calibrated Rc Oscillator
No
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Revision History
11052C–ATARM–21-Nov-11
Doc. Rev.
11052C
Doc. Rev.
11052B
Comments
HSMCI:
Added missing component.
Comments
System Controller:
Figure
ADC:
“Analog-to-Digital Converter (ADC)”
DMAC:
FIFO size table removed from
“DMA Controller
MATRIX:
Section 25.7.6.1 “EBI Chip Select Assignment
PMC:
Section 22.2 “Embedded
Then
Figure 22-2,“General Clock Block Diagram”
Section 22.3 “Master Clock
Section 22.7 “LP-DDR/DDR2
Section 22.13.11 “PMC Master Clock
UHPHS:
Section 33.2.2
introducing sentence.
Electrical Characteristics:
Section 45.12 “USB Transceiver Characteristics”
41-23 and Table 41-46).
Errata:
Section 48.1 “Boot Sequence Controller (BSC)”
programmer description.
Section 47.5 “USB High Speed Host Port (UHPHS)” removed.
- Prescaler /1,/2,/4,.../64 --> Prescaler /1,/2,/3,/4,.../64 (for Master Clock Controller.)
- SysClk DDR --> 2x MCK, and connection added above with /2 block and DDRCK.
- Value 7 for PRES field no more reserved, now with CLOCK_DIV3, Selected clock divided by 3.
- MDIV field, references to ‘SysClk DDR’ removed (x4).
DDR system clock --> DDR clock.
7-1,
“SAM9G15 System Controller Block Diagram”
“OHCI”,
0”) and DMAC1 (see
In the tables that follow, the most recent version appears first. “rfo” denotes expert input during
the update process
Figure 33-2 “Board Schematics to Interface UHP Device Controller”
Characteristics”,
Controller”, ...and the division by 6 --> ...and the division by 3.
Clock”, sentences with ‘ SysClk’ removed.
Section 31.1
updated to show Touchscreen information.
Register”:
Section 31.2.2 “DMA Controller
266MHz DDR system clock --> 133MHz DDR system clock.
“Description”, as the size depends on DMAC0 (see
:
Register”, description of NFD0_ON_D16 bitfield updated.
added as the BSC_CR register does not comply with the
added (extracted from SAM9G20 - 6384E: Section 41.7, Figure
, DDR sysclk --> DDRCK.
1”).
added, with an
Section 31.2.1
SAM9G15
Change
Request
Ref.
8074
Change
Request
Ref.
rfo
7987
8004
8008
7975
rfo
7974
8006
8016
8016
7996
rfo
1199
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