SAM9G15 Atmel Corporation, SAM9G15 Datasheet - Page 1177
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SAM9G15
Manufacturer Part Number
SAM9G15
Description
Manufacturer
Atmel Corporation
Datasheets
1.SAM9261.pdf
(248 pages)
2.SAM9261.pdf
(1274 pages)
3.SAM9261.pdf
(43 pages)
4.SAM9G15.pdf
(1211 pages)
5.SAM9G15.pdf
(45 pages)
Specifications of SAM9G15
Flash (kbytes)
0 Kbytes
Pin Count
217
Max. Operating Frequency
400 MHz
Cpu
ARM926
Hardware Qtouch Acquisition
No
Max I/o Pins
105
Ext Interrupts
105
Usb Transceiver
3
Usb Speed
Hi-Speed
Usb Interface
Host, Device
Spi
2
Twi (i2c)
3
Uart
6
Lin
4
Ssc
1
Sd / Emmc
2
Graphic Lcd
Yes
Video Decoder
No
Camera Interface
No
Adc Channels
12
Adc Resolution (bits)
10
Adc Speed (ksps)
440
Resistive Touch Screen
Yes
Temp. Sensor
No
Crypto Engine
No
Sram (kbytes)
32
Self Program Memory
NO
External Bus Interface
1
Dram Memory
DDR2/LPDDR, SDRAM/LPSDR
Nand Interface
Yes
Picopower
No
Temp. Range (deg C)
-40 to 85
I/o Supply Class
1.8/3.3
Operating Voltage (vcc)
0.9 to 1.1
Fpu
No
Mpu / Mmu
No/Yes
Timers
6
Output Compare Channels
6
Input Capture Channels
6
Pwm Channels
4
32khz Rtc
Yes
Calibrated Rc Oscillator
No
- SAM9261 PDF datasheet
- SAM9261 PDF datasheet #2
- SAM9261 PDF datasheet #3
- SAM9G15 PDF datasheet #4
- SAM9G15 PDF datasheet #5
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- Download datasheet (25Mb)
45.15 SMC Timings
45.15.1
45.15.2
45.15.2.1
45.15.2.2
Table 45-31. SMC Read Signals - NRD Controlled (READ_MODE= 1)
11052C–ATARM–21-Nov-11
Symbol
SMC
1
Timing Conditions
Timing Extraction
Zero Hold Mode Restrictions
Read Timings
Parameter
VDDIOM supply
Data Setup before NRD High
The T
(44KHz).
As a conclusion, establish VDDIOP and VDDIOM first, then VDDPLL, and VDDCORE at last, to
ensure a reliable operation of the device.
SMC Timings are given for MAX corners.
Timings are given assuming a capacitance load on data, control and address pads:
Table 45-29. Capacitance Load
In the following tables, t
Table 45-30. Zero Hold Mode Use Maximum system clock frequency (MCK)
Supply
3.3V
1.8V
Symbol
Fmax
• VDDPLL is to be established prior to VDDCORE to ensure the PLL is powered once enabled
into the ROM code.
– T
– T1 = 66 μs
– T2 = 352 μs
SLCK
RES
min (22 μs) is obtained for the maximum frequency of the internal RC oscillator
= 30 μs
Parameter
VDDIOM supply
MCK frequency
MAX
50pF
30 pF
NO HOLD SETTINGS (nrd hold = 0)
CPMCK
Corner
is MCK period.
5 pF
5 pF
MIN
Zero Hold Mode Use
1.8V
13.6
Min
1.8V
66
Min
3.3V
11.7
3.3V
66
SAM9G15
Units
Units
MHz
ns
1177
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