SAM9G15 Atmel Corporation, SAM9G15 Datasheet - Page 839
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SAM9G15
Manufacturer Part Number
SAM9G15
Description
Manufacturer
Atmel Corporation
Datasheets
1.SAM9261.pdf
(248 pages)
2.SAM9261.pdf
(1274 pages)
3.SAM9261.pdf
(43 pages)
4.SAM9G15.pdf
(1211 pages)
5.SAM9G15.pdf
(45 pages)
Specifications of SAM9G15
Flash (kbytes)
0 Kbytes
Pin Count
217
Max. Operating Frequency
400 MHz
Cpu
ARM926
Hardware Qtouch Acquisition
No
Max I/o Pins
105
Ext Interrupts
105
Usb Transceiver
3
Usb Speed
Hi-Speed
Usb Interface
Host, Device
Spi
2
Twi (i2c)
3
Uart
6
Lin
4
Ssc
1
Sd / Emmc
2
Graphic Lcd
Yes
Video Decoder
No
Camera Interface
No
Adc Channels
12
Adc Resolution (bits)
10
Adc Speed (ksps)
440
Resistive Touch Screen
Yes
Temp. Sensor
No
Crypto Engine
No
Sram (kbytes)
32
Self Program Memory
NO
External Bus Interface
1
Dram Memory
DDR2/LPDDR, SDRAM/LPSDR
Nand Interface
Yes
Picopower
No
Temp. Range (deg C)
-40 to 85
I/o Supply Class
1.8/3.3
Operating Voltage (vcc)
0.9 to 1.1
Fpu
No
Mpu / Mmu
No/Yes
Timers
6
Output Compare Channels
6
Input Capture Channels
6
Pwm Channels
4
32khz Rtc
Yes
Calibrated Rc Oscillator
No
- SAM9261 PDF datasheet
- SAM9261 PDF datasheet #2
- SAM9261 PDF datasheet #3
- SAM9G15 PDF datasheet #4
- SAM9G15 PDF datasheet #5
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39.7.8.8
Figure 39-42. Slave Node Synchronization
11052C–ATARM–21-Nov-11
Fractional Part (FP)
Fractional Part (FP)
Clcok Divider (CD)
Clcok Divider (CD)
Synchro Counter
US_LINBRR
US_LINBRR
US_BRGR
US_BRGR
LINIDRX
Clock
RXD
Slave Node Synchronization
The synchronization is done only in Slave node configuration. The procedure is based on time
measurement between falling edges of the Synch Field. The falling edges are available in dis-
tances of 2, 4, 6 and 8 bit times.
Figure 39-41. Synch Field
The time measurement is made by a 19-bit counter clocked by the sampling clock (see
39.7.1).
When the start bit of the Synch Field is detected, the counter is reset. Then during the next
8 Tbits of the Synch Field, the counter is incremented. At the end of these 8 Tbits, the counter is
stopped. At this moment, the 16 most significant bits of the counter (value divided by 8) give the
new clock divider (LINCD) and the 3 least significant bits of this value (the remainder) give the
new fractional part (LINFP).
When the Synch Field has been received, the clock divider (CD) and the fractional part (FP) are
updated in the Baud Rate Generator register (US_BRGR).
If it appears that the sampled Synch character is not equal to 0x55, then the error flag LINISFE
in the Channel Status register (US_CSR) is set to 1. It is reset by writing bit RSTSTA to 1 in the
Control register (US_CR).
The accuracy of the synchronization depends on several parameters:
• The nominal clock frequency (F
13 dominant bits (at 0)
Break Field
Initial CD
Initial CD
Initial FP
Initial FP
Start
bit
2 Tbit
1 recessive bit
Delimiter
Break
(at 1)
Reset
Start
Bit
Nom
2 Tbit
1
) (the theoretical slave node clock frequency)
0
8 Tbit
Synch Byte = 0x55
1
Synch Field
0
2 Tbit
1
0
1
0
000_0011_0001_0110_1101
2 Tbit
Stop
Bit
0000_0110_0010_1101
101
Start
Bit
ID0 ID1 ID2 ID3 ID4 ID5 ID6 ID7
Stop
bit
SAM9G15
Stop
Bit
Section
839
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