SAM9G15 Atmel Corporation, SAM9G15 Datasheet - Page 1181

• Manufacturer Part Number: SAM9G15
• Manufacturer: Atmel Corporation

Specifications of SAM9G15

• Flash (kbytes): 0 Kbytes
• Pin Count: 217
• Max. Operating Frequency: 400 MHz
• Cpu: ARM926
• Hardware Qtouch Acquisition: No
• Max I/o Pins: 105
• Ext Interrupts: 105
• Usb Transceiver: 3
• Usb Speed: Hi-Speed
• Usb Interface: Host, Device
• Spi: 2
• Twi (i2c): 3
• Uart: 6
• Lin: 4
• Ssc: 1
• Sd / Emmc: 2
• Graphic Lcd: Yes
• Video Decoder: No
• Camera Interface: No
• Adc Channels: 12
• Adc Resolution (bits): 10
• Adc Speed (ksps): 440
• Resistive Touch Screen: Yes
• Temp. Sensor: No
• Crypto Engine: No
• Sram (kbytes): 32
• Self Program Memory: NO
• External Bus Interface: 1
• Dram Memory: DDR2/LPDDR, SDRAM/LPSDR
• Nand Interface: Yes
• Picopower: No
• Temp. Range (deg C): -40 to 85
• I/o Supply Class: 1.8/3.3
• Operating Voltage (vcc): 0.9 to 1.1
• Fpu: No
• Mpu / Mmu: No/Yes
• Timers: 6
• Output Compare Channels: 6
• Input Capture Channels: 6
• Pwm Channels: 4
• 32khz Rtc: Yes
• Calibrated Rc Oscillator: No

45.16 DDRSDRC Timings
45.17 Peripheral Timings
45.17.1
45.17.1.1
45.17.1.2
11052C–ATARM–21-Nov-11
Master Write Mode
Master Read Mode
Slave Read Mode
Slave Write Mode
SPI
Maximum SPI Frequency
Timing Conditions
The DDRSDRC controller satisfies the timings of standard DDR2, LP-DDR, SDR and LP-SDR
modules.
DDR2, LP-DDR and SDR timings are specified by the JEDEC standard.
Supported speed grade limitations:
The following formulas give maximum SPI frequency in Master read and write modes and in
Slave read and write modes.
Timings are given assuming a capacitance load on
• DDR2-400 limited at 133MHz clock frequency (1.8V, 30pF on data/control, 10pF on CK/CK#)
• LP-DDR limited at 133MHz clock frequency (1.8V, 30pF on data/control, 10pF on CK)
• SDR-100 (3.3V, 50pF on data/control, 10pF on CK)
• SDR-133 (3.3V, 50pF on data/control, 10pF on CK)
• LP-SDR-133 (1.8V, 30pF on data/control, 10pF on CK)
The SPI is only sending data to a slave device such as an LCD, for example. The limit is
given by SPI
speed (see
T
DataFlash (AT45DB642D), T
This gives, F
In slave mode, SPCK is the input clock for the SPI. The max SPCK frequency is given by
setup and hold timings SPI
the pad limit, the limit in slave read mode is given by SPCK pad.
T
This gives, F
f
f
SPCK
SPCK
valid
setup
is the slave time response to output data after deleting an SPCK edge. For Atmel SPI
is the setup time from the master before sampling data (12ns).
Max
Max
=
=
Section 45.10
2
SPCK
SPCK
--------------------------------------------------------
SPI
-------------------------------------------------------- -
SPI
(or SPI
Max = 39 MHz @ VDDIO = 3.3V.
Max = 39 MHz @ VDDIO = 3.3V.
0
6
orSPI
orSPI
5
) timing. Since it gives a maximum frequency above the maximum pad
1
1
3
9
“I/Os”), the max SPI frequency is the one from the pad.
7
+
+
/SPI
valid
T
T
valid
setup
(orT
8
(or SPI
v
) is 12 ns Max.
10
/SPI
11
MISO, SPCK and MOSI
). Since this gives a frequency well above
:
SAM9G15
1181