SAM9G15 Atmel Corporation, SAM9G15 Datasheet - Page 595
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SAM9G15
Manufacturer Part Number
SAM9G15
Description
Manufacturer
Atmel Corporation
Datasheets
1.SAM9261.pdf
(248 pages)
2.SAM9261.pdf
(1274 pages)
3.SAM9261.pdf
(43 pages)
4.SAM9G15.pdf
(1211 pages)
5.SAM9G15.pdf
(45 pages)
Specifications of SAM9G15
Flash (kbytes)
0 Kbytes
Pin Count
217
Max. Operating Frequency
400 MHz
Cpu
ARM926
Hardware Qtouch Acquisition
No
Max I/o Pins
105
Ext Interrupts
105
Usb Transceiver
3
Usb Speed
Hi-Speed
Usb Interface
Host, Device
Spi
2
Twi (i2c)
3
Uart
6
Lin
4
Ssc
1
Sd / Emmc
2
Graphic Lcd
Yes
Video Decoder
No
Camera Interface
No
Adc Channels
12
Adc Resolution (bits)
10
Adc Speed (ksps)
440
Resistive Touch Screen
Yes
Temp. Sensor
No
Crypto Engine
No
Sram (kbytes)
32
Self Program Memory
NO
External Bus Interface
1
Dram Memory
DDR2/LPDDR, SDRAM/LPSDR
Nand Interface
Yes
Picopower
No
Temp. Range (deg C)
-40 to 85
I/o Supply Class
1.8/3.3
Operating Voltage (vcc)
0.9 to 1.1
Fpu
No
Mpu / Mmu
No/Yes
Timers
6
Output Compare Channels
6
Input Capture Channels
6
Pwm Channels
4
32khz Rtc
Yes
Calibrated Rc Oscillator
No
- SAM9261 PDF datasheet
- SAM9261 PDF datasheet #2
- SAM9261 PDF datasheet #3
- SAM9G15 PDF datasheet #4
- SAM9G15 PDF datasheet #5
- Current page: 595 of 1211
- Download datasheet (25Mb)
32.7.22
Name:
Address:
Access:
Note:
• CHANN_ENB: Channel Enable Status
0 = if cleared, the DMA channel no longer transfers data, and may load the next descriptor if the UDPHS_DMACONTROLx
register LDNXT_DSC bit is set.
When any transfer is ended either due to an elapsed byte count or a UDPHS device initiated transfer end, this bit is auto-
matically reset.
1 = if set, the DMA channel is currently enabled and transfers data upon request.
This bit is normally set or cleared by writing into the UDPHS_DMACONTROLx register CHANN_ENB bit field either by soft-
ware or descriptor loading.
If a channel request is currently serviced when the UDPHS_DMACONTROLx register CHANN_ENB bit is cleared, the
DMA FIFO buffer is drained until it is empty, then this status bit is cleared.
• CHANN_ACT: Channel Active Status
0 = the DMA channel is no longer trying to source the packet data.
When a packet transfer is ended this bit is automatically reset.
1 = the DMA channel is currently trying to source packet data, i.e. selected as the highest-priority requesting channel.
When a packet transfer cannot be completed due to an END_BF_ST, this flag stays set during the next channel descriptor
load (if any) and potentially until UDPHS packet transfer completion, if allowed by the new descriptor.
• END_TR_ST: End of Channel Transfer Status
0 = cleared automatically when read by software.
1 = set by hardware when the last packet transfer is complete, if the UDPHS device has ended the transfer.
Valid until the CHANN_ENB flag is cleared at the end of the next buffer transfer.
• END_BF_ST: End of Channel Buffer Status
0 = cleared automatically when read by software.
1 = set by hardware when the BUFF_COUNT downcount reach zero.
11052C–ATARM–21-Nov-11
31
23
15
–
7
–
Channel 0 is not used.
UDPHS DMA Channel Status Register
UDPHS_DMASTATUSx [x = 0..5]
0xF803C30C [0], 0xF803C31C [1], 0xF803C32C [2], 0xF803C33C [3], 0xF803C34C [4], 0xF803C35C [5]
Read-write
DESC_LDST
30
22
14
–
6
END_BF_ST
29
21
13
–
5
END_TR_ST
28
20
12
–
4
BUFF_COUNT
BUFF_COUNT
27
19
11
–
–
3
26
18
10
–
2
–
CHANN_ACT
25
17
9
–
1
SAM9G15
CHANN_ENB
24
16
8
–
0
595
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