SAM9G15 Atmel Corporation, SAM9G15 Datasheet - Page 625
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SAM9G15
Manufacturer Part Number
SAM9G15
Description
Manufacturer
Atmel Corporation
Datasheets
1.SAM9261.pdf
(248 pages)
2.SAM9261.pdf
(1274 pages)
3.SAM9261.pdf
(43 pages)
4.SAM9G15.pdf
(1211 pages)
5.SAM9G15.pdf
(45 pages)
Specifications of SAM9G15
Flash (kbytes)
0 Kbytes
Pin Count
217
Max. Operating Frequency
400 MHz
Cpu
ARM926
Hardware Qtouch Acquisition
No
Max I/o Pins
105
Ext Interrupts
105
Usb Transceiver
3
Usb Speed
Hi-Speed
Usb Interface
Host, Device
Spi
2
Twi (i2c)
3
Uart
6
Lin
4
Ssc
1
Sd / Emmc
2
Graphic Lcd
Yes
Video Decoder
No
Camera Interface
No
Adc Channels
12
Adc Resolution (bits)
10
Adc Speed (ksps)
440
Resistive Touch Screen
Yes
Temp. Sensor
No
Crypto Engine
No
Sram (kbytes)
32
Self Program Memory
NO
External Bus Interface
1
Dram Memory
DDR2/LPDDR, SDRAM/LPSDR
Nand Interface
Yes
Picopower
No
Temp. Range (deg C)
-40 to 85
I/o Supply Class
1.8/3.3
Operating Voltage (vcc)
0.9 to 1.1
Fpu
No
Mpu / Mmu
No/Yes
Timers
6
Output Compare Channels
6
Input Capture Channels
6
Pwm Channels
4
32khz Rtc
Yes
Calibrated Rc Oscillator
No
- SAM9261 PDF datasheet
- SAM9261 PDF datasheet #2
- SAM9261 PDF datasheet #3
- SAM9G15 PDF datasheet #4
- SAM9G15 PDF datasheet #5
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34.8.8.2
11052C–ATARM–21-Nov-11
11052C–ATARM–21-Nov-11
Block Length is Not Multiple of 4. (ROPT field in HSMCI_DMA register set to 0)
Two DMA Transfer descriptors are used to perform the HSMCI block transfer.
8. Poll CBTC[x] bit in the DMAC_EBCISR Register.
9. If a new list of buffer shall be transferred repeat step 6. Check and handle HSMCI
10. Poll FIFOEMPTY field in the HSMCI_SR.
11. Send The STOP_TRANSMISSION command writing the HSMCI_ARG then the
12. Wait for XFRDONE in HSMCI_SR register.
1. Use the previous step to configure the HSMCI to perform a READ_MULTIPLE_BLOCK
2. Issue a READ_MULTIPLE_BLOCK command.
3. Program the DMA Controller to use a list of descriptors.
h. Program LLI_W(n).DMAC_CFGx register for channel x with the following field’s
i.
j.
k. Program DMAC_DSCRx register for channel x with the address of LLI_W(0).
l.
errors.
HSMCI_CMDR.
command.
a. Read the channel register to choose an available (disabled) channel.
b. Clear any pending interrupts on the channel from the previous DMAC transfer by
c. For every block of data repeat the following procedure:
d. Program the channel registers in the Memory for the first descriptor. This descriptor
e. The LLI_W(n).DMAC_SADDRx field in memory must be set with the starting
f.
g. Program LLI_W(n).DMAC_CTRLAx with the following field’s values:
values:
–FIFOCFG defines the watermark of the DMA channel FIFO.
–DST_REP is set to zero. Addresses are contiguous.
–SRC_H2SEL is set to true to enable hardware handshaking on the destination.
–SRC_PER is programmed with the hardware handshaking ID of the targeted
Program LLI_W(n).DMAC_DSCRx with the address of LLI_W(n+1) descriptor. And
set the DSCRx_IF to the AHB Layer ID. This operation actually links descriptors
together. If LLI_W(n) is the last descriptor then LLI_W(n).DMAC_DSCRx points to
0.
Program DMAC_CTRLBx register for channel x with 0. its content is updated with
the LLI Fetch operation.
Enable Channel x writing one to DMAC_CHER[x]. The DMA is ready and waiting
for request.
reading the DMAC_EBCISR register.
will be word oriented. This descriptor is referred to as LLI_W(n) standing for LLI
word oriented transfer for block n.
address of the HSMCI_FIFO address.
The LLI_W(n).DMAC_DADDRx field in the memory must be word aligned.
–DST_WIDTH is set to WORD.
–SRC_WIDTH is set to WORD.
–SCSIZE must be set according to the value of HSMCI_DMA, CHKSIZE field.
–BTSIZE is programmed with block_length/4. If BTSIZE is zero, this descriptor is
HSMCI Host Controller.
skipped later.
SAM9G15
SAM9G15
625
625
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